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High-density vertical sidewall MoS2 transistors through T-shape vertical lamination

Author

Listed:
  • Quanyang Tao

    (Hunan University
    Hunan University)

  • Ruixia Wu

    (Hunan University
    Hunan University)

  • Xuming Zou

    (Hunan University)

  • Yang Chen

    (Hunan University)

  • Wanying Li

    (Hunan University)

  • Zheyi Lu

    (Hunan University)

  • Likuan Ma

    (Hunan University)

  • Lingan Kong

    (Hunan University)

  • Donglin Lu

    (Hunan University)

  • Xiaokun Yang

    (Hunan University)

  • Wenjing Song

    (Hunan University)

  • Wei Li

    (Hunan University)

  • Liting Liu

    (Hunan University)

  • Shuimei Ding

    (Hunan University)

  • Xiao Liu

    (Hunan University)

  • Xidong Duan

    (Hunan University)

  • Lei Liao

    (Hunan University)

  • Yuan Liu

    (Hunan University)

Abstract

Vertical transistors, in which the source and drain are aligned vertically and the current flow is normal to the wafer surface, have attracted considerable attention recently. However, the realization of high-density vertical transistors is challenging, and could be largely attributed to the incompatibility between vertical structures and conventional lateral fabrication processes. Here we report a T-shape lamination approach for realizing high-density vertical sidewall transistors, where lateral transistors could be pre-fabricated on planar substrates first and then laminated onto vertical substrates using T-shape stamps, hence overcoming the incompatibility between planar processes and vertical structures. Based on this technique, we vertically stacked 60 MoS2 transistors within a small vertical footprint, corresponding to a device density over 108 cm−2. Furthermore, we demonstrate two approaches for scalable fabrication of vertical sidewall transistor arrays, including simultaneous lamination onto multiple vertical substrates, as well as on the same vertical substrate using multi-cycle layer-by-layer laminations.

Suggested Citation

  • Quanyang Tao & Ruixia Wu & Xuming Zou & Yang Chen & Wanying Li & Zheyi Lu & Likuan Ma & Lingan Kong & Donglin Lu & Xiaokun Yang & Wenjing Song & Wei Li & Liting Liu & Shuimei Ding & Xiao Liu & Xidong , 2024. "High-density vertical sidewall MoS2 transistors through T-shape vertical lamination," Nature Communications, Nature, vol. 15(1), pages 1-7, December.
  • Handle: RePEc:nat:natcom:v:15:y:2024:i:1:d:10.1038_s41467-024-50185-4
    DOI: 10.1038/s41467-024-50185-4
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    References listed on IDEAS

    as
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