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Monolithic three-dimensional tier-by-tier integration via van der Waals lamination

Author

Listed:
  • Donglin Lu

    (Hunan University)

  • Yang Chen

    (Hunan University)

  • Zheyi Lu

    (Hunan University)

  • Likuan Ma

    (Hunan University)

  • Quanyang Tao

    (Hunan University)

  • Zhiwei Li

    (Hunan University)

  • Lingan Kong

    (Hunan University)

  • Liting Liu

    (Hunan University)

  • Xiaokun Yang

    (Hunan University)

  • Shuimei Ding

    (Hunan University)

  • Xiao Liu

    (Hunan University)

  • Yunxin Li

    (Hunan University)

  • Ruixia Wu

    (Hunan University
    Hunan University)

  • Yiliu Wang

    (Hunan University)

  • Yuanyuan Hu

    (Hunan University)

  • Xidong Duan

    (Hunan University)

  • Lei Liao

    (Hunan University)

  • Yuan Liu

    (Hunan University)

Abstract

Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching1–10. However, with atomically thin body thickness, 2D semiconductors are not compatible with various high-energy processes in microelectronics11–13, where the M3D integration of multiple 2D circuit tiers is challenging. Here we report an alternative low-temperature M3D integration approach by van der Waals (vdW) lamination of entire prefabricated circuit tiers, where the processing temperature is controlled to 120 °C. By further repeating the vdW lamination process tier by tier, an M3D integrated system is achieved with 10 circuit tiers in the vertical direction, overcoming previous thermal budget limitations. Detailed electrical characterization demonstrates the bottom 2D transistor is not impacted after repetitively laminating vdW circuit tiers on top. Furthermore, by vertically connecting devices within different tiers through vdW inter-tier vias, various logic and heterogeneous structures are realized with desired system functions. Our demonstration provides a low-temperature route towards fabricating M3D circuits with increased numbers of tiers.

Suggested Citation

  • Donglin Lu & Yang Chen & Zheyi Lu & Likuan Ma & Quanyang Tao & Zhiwei Li & Lingan Kong & Liting Liu & Xiaokun Yang & Shuimei Ding & Xiao Liu & Yunxin Li & Ruixia Wu & Yiliu Wang & Yuanyuan Hu & Xidong, 2024. "Monolithic three-dimensional tier-by-tier integration via van der Waals lamination," Nature, Nature, vol. 630(8016), pages 340-345, June.
  • Handle: RePEc:nat:nature:v:630:y:2024:i:8016:d:10.1038_s41586-024-07406-z
    DOI: 10.1038/s41586-024-07406-z
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    Cited by:

    1. Xiaokun Yang & Rui He & Zheyi Lu & Yang Chen & Liting Liu & Donglin Lu & Likuan Ma & Quanyang Tao & Lingan Kong & Zhaojing Xiao & Songlong Liu & Zhiwei Li & Shuimei Ding & Xiao Liu & Yunxin Li & Yiliu, 2024. "Large-scale sub-5-nm vertical transistors by van der Waals integration," Nature Communications, Nature, vol. 15(1), pages 1-8, December.

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