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Large-scale sub-5-nm vertical transistors by van der Waals integration

Author

Listed:
  • Xiaokun Yang

    (Hunan University)

  • Rui He

    (Hunan University
    Hunan University)

  • Zheyi Lu

    (Hunan University)

  • Yang Chen

    (Hunan University)

  • Liting Liu

    (Hunan University)

  • Donglin Lu

    (Hunan University)

  • Likuan Ma

    (Hunan University)

  • Quanyang Tao

    (Hunan University)

  • Lingan Kong

    (Hunan University)

  • Zhaojing Xiao

    (Hunan University)

  • Songlong Liu

    (Hunan University)

  • Zhiwei Li

    (Hunan University)

  • Shuimei Ding

    (Hunan University)

  • Xiao Liu

    (Hunan University)

  • Yunxin Li

    (Hunan University)

  • Yiliu Wang

    (Hunan University)

  • Lei Liao

    (Hunan University)

  • Yuan Liu

    (Hunan University)

Abstract

Vertical field effect transistor (VFET), in which the semiconductor is sandwiched between source/drain electrodes and the channel length is simply determined by the semiconductor thickness, has demonstrated promising potential for short channel devices. However, despite extensive efforts over the past decade, scalable methods to fabricate ultra-short channel VFETs remain challenging. Here, we demonstrate a layer-by-layer transfer process of large-scale indium gallium zinc oxide (IGZO) semiconductor arrays and metal electrodes, and realize large-scale VFETs with ultra-short channel length and high device performance. Within this process, the oxide semiconductor could be pre-deposited on a sacrificial wafer, and then physically released and sandwiched between metals, maintaining the intrinsic properties of ultra-scaled vertical channel. Based on this lamination process, we realize 2 inch-scale VFETs with channel length down to 4 nm, on-current over 800 A/cm2, and highest on-off ratio up to 2 × 105, which is over two orders of magnitude higher compared to control samples without laminating process. Our study not only represents the optimization of VFETs performance and scalability at the same time, but also offers a method of transfer large-scale oxide arrays, providing interesting implication for ultra-thin vertical devices.

Suggested Citation

  • Xiaokun Yang & Rui He & Zheyi Lu & Yang Chen & Liting Liu & Donglin Lu & Likuan Ma & Quanyang Tao & Lingan Kong & Zhaojing Xiao & Songlong Liu & Zhiwei Li & Shuimei Ding & Xiao Liu & Yunxin Li & Yiliu, 2024. "Large-scale sub-5-nm vertical transistors by van der Waals integration," Nature Communications, Nature, vol. 15(1), pages 1-8, December.
  • Handle: RePEc:nat:natcom:v:15:y:2024:i:1:d:10.1038_s41467-024-52150-7
    DOI: 10.1038/s41467-024-52150-7
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    References listed on IDEAS

    as
    1. Wei Cao & Huiming Bu & Maud Vinet & Min Cao & Shinichi Takagi & Sungwoo Hwang & Tahir Ghani & Kaustav Banerjee, 2023. "The future transistors," Nature, Nature, vol. 620(7974), pages 501-515, August.
    2. Yuan Liu & Xidong Duan & Hyeon-Jin Shin & Seongjun Park & Yu Huang & Xiangfeng Duan, 2021. "Promises and prospects of two-dimensional transistors," Nature, Nature, vol. 591(7848), pages 43-53, March.
    3. Donglin Lu & Yang Chen & Zheyi Lu & Likuan Ma & Quanyang Tao & Zhiwei Li & Lingan Kong & Liting Liu & Xiaokun Yang & Shuimei Ding & Xiao Liu & Yunxin Li & Ruixia Wu & Yiliu Wang & Yuanyuan Hu & Xidong, 2024. "Monolithic three-dimensional tier-by-tier integration via van der Waals lamination," Nature, Nature, vol. 630(8016), pages 340-345, June.
    4. Wei Cao & Huiming Bu & Maud Vinet & Min Cao & Shinichi Takagi & Sungwoo Hwang & Tahir Ghani & Kaustav Banerjee, 2023. "Publisher Correction: The future transistors," Nature, Nature, vol. 621(7979), pages 43-43, September.
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