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The future transistors

Author

Listed:
  • Wei Cao

    (University of California Santa Barbara)

  • Huiming Bu

    (IBM Research)

  • Maud Vinet

    (Université Grenoble Alpes, CEA-LETI)

  • Min Cao

    (Pathfinding, Taiwan Semiconductor Manufacturing Company)

  • Shinichi Takagi

    (The University of Tokyo)

  • Sungwoo Hwang

    (Samsung Advanced Institute of Technology)

  • Tahir Ghani

    (Pathfinding and Technology Definition, Intel Corporation)

  • Kaustav Banerjee

    (University of California Santa Barbara)

Abstract

The metal–oxide–semiconductor field-effect transistor (MOSFET), a core element of complementary metal–oxide–semiconductor (CMOS) technology, represents one of the most momentous inventions since the industrial revolution. Driven by the requirements for higher speed, energy efficiency and integration density of integrated-circuit products, in the past six decades the physical gate length of MOSFETs has been scaled to sub-20 nanometres. However, the downscaling of transistors while keeping the power consumption low is increasingly challenging, even for the state-of-the-art fin field-effect transistors. Here we present a comprehensive assessment of the existing and future CMOS technologies, and discuss the challenges and opportunities for the design of FETs with sub-10-nanometre gate length based on a hierarchical framework established for FET scaling. We focus our evaluation on identifying the most promising sub-10-nanometre-gate-length MOSFETs based on the knowledge derived from previous scaling efforts, as well as the research efforts needed to make the transistors relevant to future logic integrated-circuit products. We also detail our vision of beyond-MOSFET future transistors and potential innovation opportunities. We anticipate that innovations in transistor technologies will continue to have a central role in driving future materials, device physics and topology, heterogeneous vertical and lateral integration, and computing technologies.

Suggested Citation

  • Wei Cao & Huiming Bu & Maud Vinet & Min Cao & Shinichi Takagi & Sungwoo Hwang & Tahir Ghani & Kaustav Banerjee, 2023. "The future transistors," Nature, Nature, vol. 620(7974), pages 501-515, August.
  • Handle: RePEc:nat:nature:v:620:y:2023:i:7974:d:10.1038_s41586-023-06145-x
    DOI: 10.1038/s41586-023-06145-x
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    Cited by:

    1. Holly G. Stemp & Serwan Asaad & Mark R. van Blankenstein & Arjen Vaartjes & Mark A. I. Johnson & Mateusz T. Mądzik & Amber J. A. Heskes & Hannes R. Firgau & Rocky Y. Su & Chih Hwan Yang & Arne Laucht , 2024. "Tomography of entangling two-qubit logic operations in exchange-coupled donor electron spin qubits," Nature Communications, Nature, vol. 15(1), pages 1-10, December.
    2. Baracani, Manuela & Favoino, Fabio & Fantucci, Stefano & Serra, Valentina & Perino, Marco & Introna, Marisandra & Limbach, Rene & Wondraczek, Lothar, 2023. "Experimental assessment of the energy performance of microfluidic glazing components: The first results of a monitoring campaign carried out in an outdoor test facility," Energy, Elsevier, vol. 280(C).
    3. Arnab Pal & Zichun Chai & Junkai Jiang & Wei Cao & Mike Davies & Vivek De & Kaustav Banerjee, 2024. "An ultra energy-efficient hardware platform for neuromorphic computing enabled by 2D-TMD tunnel-FETs," Nature Communications, Nature, vol. 15(1), pages 1-10, December.
    4. Xiaokun Yang & Rui He & Zheyi Lu & Yang Chen & Liting Liu & Donglin Lu & Likuan Ma & Quanyang Tao & Lingan Kong & Zhaojing Xiao & Songlong Liu & Zhiwei Li & Shuimei Ding & Xiao Liu & Yunxin Li & Yiliu, 2024. "Large-scale sub-5-nm vertical transistors by van der Waals integration," Nature Communications, Nature, vol. 15(1), pages 1-8, December.

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