Current limiting strategies for grid forming inverters under low voltage ride through

Grid forming inverters are expected to play a key role in future power grids, replacing synchronous generator-based plants. However, the limited current capability of power electronics makes a difference when facing fault induced voltage sags. This work provides a comprehensive review of strategies to handle low voltage ride through events in grid forming inverters. A key contribution of this work is to differentiate between current limiting and transient stability enhancing strategies. Current limiting strategies are classified into voltage and current-based approaches according to the inverter behaviour during the fault. Their performance is evaluated attending to three criteria: (1) transient current limitation capability, related to the self-preservation of the device; and (2) fault current management and (3) transient synchronization stability, key aspects to meet grid code requirements. The modifications that are required to support the grid under asymmetrical faults are also described, focusing on the management and prioritization of positive and negative-sequence fault currents. Transient stability enhancing strategies are classified according to their implementation into (1) power synchronization loop-based and (2) current saturation-based approaches. Their main characteristics are highlighted and compared, whereas their compatibility with previous current limiting strategies is also discussed. Finally, identified open issues and challenges are covered.