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Wafer map defect pattern classification based on convolutional neural network features and error-correcting output codes

Author

Listed:
  • Cheng Hao Jin

    (ENN Research Institute of Digital Technology)

  • Hyun-Jin Kim

    (BISTel)

  • Yongjun Piao

    (Nankai University)

  • Meijing Li

    (Shanghai Maritime University)

  • Minghao Piao

    (Chungbuk National University)

Abstract

Defect clusters on the wafer map can provide important clue to identify the process failures so that it is important to accurately classify the defect patterns into corresponding pattern types. In this research, we present an image-based wafer map defect pattern classification method. The presented method consists of two main steps: without any specific preprocessing, high-level features are extracted from convolutional neural network and then the extracted features are fed to combination of error-correcting output codes and support vector machines for wafer map defect pattern classification. To the best of our knowledge, no prior work has applied the presented method for wafer map defect pattern classification. Experimental results tested on 20,000 wafer maps show the superiority of presented method and the overall classification accuracy is up to 98.43%.

Suggested Citation

  • Cheng Hao Jin & Hyun-Jin Kim & Yongjun Piao & Meijing Li & Minghao Piao, 2020. "Wafer map defect pattern classification based on convolutional neural network features and error-correcting output codes," Journal of Intelligent Manufacturing, Springer, vol. 31(8), pages 1861-1875, December.
    • Handle: RePEc:spr:joinma:v:31:y:2020:i:8:d:10.1007_s10845-020-01540-x
    DOI: 10.1007/s10845-020-01540-x
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    References listed on IDEAS

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    1. Hui Lin & Bin Li & Xinggang Wang & Yufeng Shu & Shuanglong Niu, 2019. "Automated defect inspection of LED chip using deep convolutional neural network," Journal of Intelligent Manufacturing, Springer, vol. 30(6), pages 2525-2534, August.
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    Cited by:

    1. Chia-Yu Hsu & Ju-Chien Chien, 2022. "Ensemble convolutional neural networks with weighted majority for wafer bin map pattern classification," Journal of Intelligent Manufacturing, Springer, vol. 33(3), pages 831-844, March.
    2. Minyoung Lee & Joohyoung Jeon & Hongchul Lee, 2022. "Explainable AI for domain experts: a post Hoc analysis of deep learning for defect classification of TFT–LCD panels," Journal of Intelligent Manufacturing, Springer, vol. 33(6), pages 1747-1759, August.
    3. Feng Huang & Ben-wu Wang & Qi-peng Li & Jun Zou, 2023. "Texture surface defect detection of plastic relays with an enhanced feature pyramid network," Journal of Intelligent Manufacturing, Springer, vol. 34(3), pages 1409-1425, March.
    4. Chengjun Xu & Guobin Zhu, 2021. "Intelligent manufacturing Lie Group Machine Learning: real-time and efficient inspection system based on fog computing," Journal of Intelligent Manufacturing, Springer, vol. 32(1), pages 237-249, January.
    5. Tongwha Kim & Kamran Behdinan, 2023. "Advances in machine learning and deep learning applications towards wafer map defect recognition and classification: a review," Journal of Intelligent Manufacturing, Springer, vol. 34(8), pages 3215-3247, December.
    6. Minghao Piao & Cheng Hao Jin, 2023. "CNN and ensemble learning based wafer map failure pattern recognition based on local property based features," Journal of Intelligent Manufacturing, Springer, vol. 34(8), pages 3599-3621, December.

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