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CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor

Author

Listed:
  • Wenhui Wang

    (Southern University of Science and Technology)

  • Ke Li

    (Southern University of Science and Technology)

  • Jun Lan

    (Southern University of Science and Technology)

  • Mei Shen

    (Southern University of Science and Technology)

  • Zhongrui Wang

    (The University of Hong Kong)

  • Xuewei Feng

    (Shanghai Jiao Tong University)

  • Hongyu Yu

    (Southern University of Science and Technology)

  • Kai Chen

    (Southern University of Science and Technology)

  • Jiamin Li

    (Southern University of Science and Technology)

  • Feichi Zhou

    (Southern University of Science and Technology)

  • Longyang Lin

    (Southern University of Science and Technology)

  • Panpan Zhang

    (Beijing University of Posts and Telecommunications)

  • Yida Li

    (Southern University of Science and Technology)

Abstract

The development of high-performance oxide-based transistors is critical to enable very large-scale integration (VLSI) of monolithic 3-D integrated circuit (IC) in complementary metal oxide semiconductor (CMOS) backend-of-line (BEOL). Atomic layer deposition (ALD) deposited ZnO is an attractive candidate due to its excellent electrical properties, low processing temperature below copper interconnect thermal budget, and conformal sidewall deposition for novel 3D architecture. An optimized ALD deposited ZnO thin-film transistor achieving a record field-effect and intrinsic mobility (µFE /µo) of 85/140 cm2/V·s is presented here. The ZnO TFT was integrated with HfO2 RRAM in a 1 kbit (32 × 32) 1T1R array, demonstrating functionalities in RRAM switching. In order to co-design for future technology requiring high performance BEOL circuitries implementation, a spice-compatible model of the ZnO TFTs was developed. We then present designs of various ZnO TFT-based inverters, and 5-stage ring oscillators through simulations and experiments with working frequency exceeding 10’s of MHz.

Suggested Citation

  • Wenhui Wang & Ke Li & Jun Lan & Mei Shen & Zhongrui Wang & Xuewei Feng & Hongyu Yu & Kai Chen & Jiamin Li & Feichi Zhou & Longyang Lin & Panpan Zhang & Yida Li, 2023. "CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor," Nature Communications, Nature, vol. 14(1), pages 1-11, December.
    • Handle: RePEc:nat:natcom:v:14:y:2023:i:1:d:10.1038_s41467-023-41868-5
    DOI: 10.1038/s41467-023-41868-5
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    References listed on IDEAS

    as
    1. Max M. Shulaker & Gage Hills & Rebecca S. Park & Roger T. Howe & Krishna Saraswat & H.-S. Philip Wong & Subhasish Mitra, 2017. "Three-dimensional integration of nanotechnologies for computing and data storage on a single chip," Nature, Nature, vol. 547(7661), pages 74-78, July.
    2. Maheswari Sivan & Yida Li & Hasita Veluri & Yunshan Zhao & Baoshan Tang & Xinghua Wang & Evgeny Zamburg & Jin Feng Leong & Jessie Xuhua Niu & Umesh Chand & Aaron Voon-Yew Thean, 2019. "All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration," Nature Communications, Nature, vol. 10(1), pages 1-12, December.
    3. Baoshan Tang & Hasita Veluri & Yida Li & Zhi Gen Yu & Moaz Waqar & Jin Feng Leong & Maheswari Sivan & Evgeny Zamburg & Yong-Wei Zhang & John Wang & Aaron V-Y. Thean, 2022. "Wafer-scale solution-processed 2D material analog resistive memory array for memory-based computing," Nature Communications, Nature, vol. 13(1), pages 1-9, December.
    4. Yang Liu & Sheng Wang & Huaping Liu & Lian-Mao Peng, 2017. "Carbon nanotube-based three-dimensional monolithic optoelectronic integrated system," Nature Communications, Nature, vol. 8(1), pages 1-8, August.
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