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All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration

Author

Listed:
  • Maheswari Sivan

    (National University of Singapore)

  • Yida Li

    (National University of Singapore)

  • Hasita Veluri

    (National University of Singapore)

  • Yunshan Zhao

    (National University of Singapore)

  • Baoshan Tang

    (National University of Singapore)

  • Xinghua Wang

    (National University of Singapore)

  • Evgeny Zamburg

    (National University of Singapore)

  • Jin Feng Leong

    (National University of Singapore)

  • Jessie Xuhua Niu

    (National University of Singapore)

  • Umesh Chand

    (National University of Singapore)

  • Aaron Voon-Yew Thean

    (National University of Singapore)

Abstract

3D monolithic integration of logic and memory has been the most sought after solution to surpass the Von Neumann bottleneck, for which a low-temperature processed material system becomes inevitable. Two-dimensional materials, with their excellent electrical properties and low thermal budget are potential candidates. Here, we demonstrate a low-temperature hybrid co-integration of one-transistor-one-resistor memory cell, comprising a surface functionalized 2D WSe2 p-FET, with a solution-processed WSe2 Resistive Random Access Memory. The employed plasma oxidation technique results in a low Schottky barrier height of 25 meV with a mobility of 230 cm2 V−1 s−1, leading to a 100x performance enhanced WSe2 p-FET, while the defective WSe2 Resistive Random Access Memory exhibits a switching energy of 2.6 pJ per bit. Furthermore, guided by our device-circuit modelling, we propose vertically stacked channel FETs for high-density sub-0.01 μm2 memory cells, offering a new beyond-Si solution to enable 3-D embedded memories for future computing systems.

Suggested Citation

  • Maheswari Sivan & Yida Li & Hasita Veluri & Yunshan Zhao & Baoshan Tang & Xinghua Wang & Evgeny Zamburg & Jin Feng Leong & Jessie Xuhua Niu & Umesh Chand & Aaron Voon-Yew Thean, 2019. "All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration," Nature Communications, Nature, vol. 10(1), pages 1-12, December.
    • Handle: RePEc:nat:natcom:v:10:y:2019:i:1:d:10.1038_s41467-019-13176-4
    DOI: 10.1038/s41467-019-13176-4
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    Cited by:

    1. Wenhui Wang & Ke Li & Jun Lan & Mei Shen & Zhongrui Wang & Xuewei Feng & Hongyu Yu & Kai Chen & Jiamin Li & Feichi Zhou & Longyang Lin & Panpan Zhang & Yida Li, 2023. "CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor," Nature Communications, Nature, vol. 14(1), pages 1-11, December.
    2. Maosong Xie & Yueyang Jia & Chen Nie & Zuheng Liu & Alvin Tang & Shiquan Fan & Xiaoyao Liang & Li Jiang & Zhezhi He & Rui Yang, 2023. "Monolithic 3D integration of 2D transistors and vertical RRAMs in 1T–4R structure for high-density memory," Nature Communications, Nature, vol. 14(1), pages 1-11, December.

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