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Scheduling semiconductor test operations: Minimizing maximum lateness and number of tardy jobs on a single machine

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  • Reha Uzsoy
  • Chung‐Yee Lee
  • Louis A. Martin‐Vega

Abstract

We examine a class of single‐machine scheduling problems with sequence‐dependent setup times that arise in the context of semiconductor test operations. We present heuristics for the problems of minimizing maximum lateness with dynamic arrivals and minimizing number of tardy jobs. We exploit special problem structure to derive worst‐case error bounds. The special problem structure also enables us to derive dynamic programming procedures for the problems where all jobs are available simultaneously.

Suggested Citation

  • Reha Uzsoy & Chung‐Yee Lee & Louis A. Martin‐Vega, 1992. "Scheduling semiconductor test operations: Minimizing maximum lateness and number of tardy jobs on a single machine," Naval Research Logistics (NRL), John Wiley & Sons, vol. 39(3), pages 369-388, April.
    • Handle: RePEc:wly:navres:v:39:y:1992:i:3:p:369-388
    DOI: 10.1002/1520-6750(199204)39:33.0.CO;2-F
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    Cited by:

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    2. Yu, Tae-Sun & Han, Jun-Hee, 2021. "Scheduling proportionate flow shops with preventive machine maintenance," International Journal of Production Economics, Elsevier, vol. 231(C).

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