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Exact and efficient reliability and performance optimization of synchronous task graphs

Author

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  • Ramezani, Reza
  • Ghavidel, Abolfazl
  • Sedaghat, Yasser

Abstract

SRAM-based FPGAs have found many applications in modern computer systems. In these systems, high-performance computing applications are executed as task graphs in which reliability and performance are crucial constraints. In this paper, an exact method is presented to efficiently optimize the reliability and performance of synchronous task graphs running on SRAM-based FPGAs in harsh environments. Solving this optimization problem leads to the generation of a true Pareto set of Fault Tolerance (FT) techniques. Each solution of this set determines FT techniques of the tasks and leads to specific reliability and makespan. Thus, this solution set trades off between reliability and makespan, and one of the solutions that best meets system requirements can be applied to the running tasks to optimize the reliability and performance. The proposed technique is novel as it obtains the true Pareto set of FT techniques of the whole task graph by partitioning the task graph into its segments, optimizing different segments separately, and joining the obtained solutions. This partitioning strategy leads to reduce the computation time significantly. In this paper, it is mathematically proved that the proposed partitioning strategy generates global optima from the local ones without losing any optimal solutions. The experiments show that the proposed technique improves the MTTF of real-world and random task graphs by 46.30% on average without any negative effects on the performance. Then, the efficiency of the computation time of the proposed technique is demonstrated by conducting several experiments on small-, medium-, and large-size synchronous task graphs and comparing the results with other exact and evolutionary optimization methods. Finally, supplementary experiments in dynamic environments show that the proposed technique outperforms adaptive state-of-the-art FT techniques in terms of reliability and makespan improvement.

Suggested Citation

  • Ramezani, Reza & Ghavidel, Abolfazl & Sedaghat, Yasser, 2021. "Exact and efficient reliability and performance optimization of synchronous task graphs," Reliability Engineering and System Safety, Elsevier, vol. 205(C).
  • Handle: RePEc:eee:reensy:v:205:y:2021:i:c:s0951832020307249
    DOI: 10.1016/j.ress.2020.107223
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    References listed on IDEAS

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    1. Zhao, Jian-Hua & Liu, Zhaoheng & Dao, My-Thien, 2007. "Reliability optimization using multiobjective ant colony system approaches," Reliability Engineering and System Safety, Elsevier, vol. 92(1), pages 109-120.
    2. Ramezani, Reza & Sedaghat, Yasser & Naghibzadeh, Mahmoud & Clemente, Juan Antonio, 2018. "A decomposition-based reliability and makespan optimization technique for hardware task graphs," Reliability Engineering and System Safety, Elsevier, vol. 180(C), pages 13-24.
    3. Hoque, Khaza Anuarul & Ait Mohamed, Otmane & Savaria, Yvon, 2019. "Dependability modeling and optimization of triple modular redundancy partitioning for SRAM-based FPGAs," Reliability Engineering and System Safety, Elsevier, vol. 182(C), pages 107-119.
    4. Jung, Seunghwa & Choi, Jihwan P., 2019. "Predicting system failure rates of SRAM-based FPGA on-board processors in space radiation environments," Reliability Engineering and System Safety, Elsevier, vol. 183(C), pages 374-386.
    5. Khalili-Damghani, Kaveh & Abtahi, Amir-Reza & Tavana, Madjid, 2013. "A new multi-objective particle swarm optimization method for solving reliability redundancy allocation problems," Reliability Engineering and System Safety, Elsevier, vol. 111(C), pages 58-75.
    6. Kretzschmar, U. & Gomez-Cornejo, J. & Astarloa, A. & Bidarte, U. & Ser, J. Del, 2016. "Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs," Reliability Engineering and System Safety, Elsevier, vol. 151(C), pages 1-9.
    7. Villalta, Igor & Bidarte, Unai & Gómez-Cornejo, Julen & Jiménez, Jaime & Lázaro, Jesús, 2018. "SEU emulation in industrial SoCs combining microprocessor and FPGA," Reliability Engineering and System Safety, Elsevier, vol. 170(C), pages 53-63.
    8. Ramezani, Reza & Clemente, Juan Antonio & Franco, Francisco J., 2020. "Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets," Reliability Engineering and System Safety, Elsevier, vol. 202(C).
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