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A case study on the multistage IC final testing scheduling problem with reentry

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  • Pearn, W. L.
  • Chung, S. H.
  • Chen, A. Y.
  • Yang, M. H.

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  • Pearn, W. L. & Chung, S. H. & Chen, A. Y. & Yang, M. H., 2004. "A case study on the multistage IC final testing scheduling problem with reentry," International Journal of Production Economics, Elsevier, vol. 88(3), pages 257-267, April.
    • Handle: RePEc:eee:proeco:v:88:y:2004:i:3:p:257-267
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    References listed on IDEAS

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    1. Yalaoui, Farouk & Chu, Chengbin, 2002. "Parallel machine scheduling to minimize total tardiness," International Journal of Production Economics, Elsevier, vol. 76(3), pages 265-279, April.
    2. Potvin, Jean-Yves & Rousseau, Jean-Marc, 1993. "A parallel route building algorithm for the vehicle routing and scheduling problem with time windows," European Journal of Operational Research, Elsevier, vol. 66(3), pages 331-340, May.
    3. W L Pearn & S H Chung & M H Yang, 2002. "The wafer probing scheduling problem (WPSP)," Journal of the Operational Research Society, Palgrave Macmillan;The OR Society, vol. 53(8), pages 864-874, August.
    4. Kemal Altinkemer & Bezalel Gavish, 1991. "Parallel Savings Based Heuristics for the Delivery Problem," Operations Research, INFORMS, vol. 39(3), pages 456-469, June.
    5. Schutten, J. M. J. & Leussink, R. A. M., 1996. "Parallel machine scheduling with release dates, due dates and family setup times," International Journal of Production Economics, Elsevier, vol. 46(1), pages 119-125, December.
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    Cited by:

    1. S-W Choi & Y-D Kim, 2007. "Minimizing makespan on a two-machine re-entrant flowshop," Journal of the Operational Research Society, Palgrave Macmillan;The OR Society, vol. 58(7), pages 972-981, July.
    2. Choi, Seong-Woo & Kim, Yeong-Dae, 2009. "Minimizing total tardiness on a two-machine re-entrant flowshop," European Journal of Operational Research, Elsevier, vol. 199(2), pages 375-384, December.
    3. Hyun Joong Yoon & Junjae Chae, 2019. "Simulation Study for Semiconductor Manufacturing System: Dispatching Policies for a Wafer Test Facility," Sustainability, MDPI, vol. 11(4), pages 1-21, February.
    4. Zhang, Zhicong & Zheng, Li & Hou, Forest & Li, Na, 2011. "Semiconductor final test scheduling with Sarsa([lambda], k) algorithm," European Journal of Operational Research, Elsevier, vol. 215(2), pages 446-458, December.
    5. Allahverdi, Ali & Ng, C.T. & Cheng, T.C.E. & Kovalyov, Mikhail Y., 2008. "A survey of scheduling problems with setup times or costs," European Journal of Operational Research, Elsevier, vol. 187(3), pages 985-1032, June.
    6. Allahverdi, Ali & Soroush, H.M., 2008. "The significance of reducing setup times/setup costs," European Journal of Operational Research, Elsevier, vol. 187(3), pages 978-984, June.

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