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Hierarchical Transfer Learning for Cycle Time Forecasting for Semiconductor Wafer Lot under Different Work in Process Levels

Author

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  • Junliang Wang

    (Institute of Artificial Intelligence, Donghua University, Shanghai 201620, China)

  • Pengjie Gao

    (Institute of Artificial Intelligence, Donghua University, Shanghai 201620, China)

  • Zhe Li

    (Institute of Artificial Intelligence, Donghua University, Shanghai 201620, China)

  • Wei Bai

    (State Key Laboratory of Digital Manufacturing Equipment and Technology, Huazhong University of Science and Technology, Wuhan 430074, China
    Shenzhen Huazhong University of Science and Technology Research Institute, Shenzhen 518000, China)

Abstract

The accurate cycle time (CT) prediction of the wafer fabrication remains a tough task, as the system level of work in process (WIP) is fluctuant. Aiming to construct one unified CT forecasting model under dynamic WIP levels, this paper proposes a transfer learning method for finetuning the predicted neural network hierarchically. First, a two-dimensional (2D) convolutional neural network was constructed to predict the CT under a primary WIP level with the input of spatial-temporal characteristics by reorganizing the input parameters. Then, to predict the CT under another WIP level, a hierarchical optimization transfer learning strategy was designed to finetune the prediction model so as to improve the accuracy of the CT forecasting. The experimental results demonstrated that the hierarchically transfer learning approach outperforms the compared methods in the CT forecasting with the fluctuation of WIP levels.

Suggested Citation

  • Junliang Wang & Pengjie Gao & Zhe Li & Wei Bai, 2021. "Hierarchical Transfer Learning for Cycle Time Forecasting for Semiconductor Wafer Lot under Different Work in Process Levels," Mathematics, MDPI, vol. 9(17), pages 1-11, August.
    • Handle: RePEc:gam:jmathe:v:9:y:2021:i:17:p:2039-:d:621267
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    References listed on IDEAS

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    1. Lars Mönch & Reha Uzsoy & John W. Fowler, 2018. "A survey of semiconductor supply chain models part III: master planning, production planning, and demand fulfilment," International Journal of Production Research, Taylor & Francis Journals, vol. 56(13), pages 4565-4584, July.
    2. Feng Yang & Bruce E. Ankenman & Barry L. Nelson, 2008. "Estimating Cycle Time Percentile Curves for Manufacturing Systems via Simulation," INFORMS Journal on Computing, INFORMS, vol. 20(4), pages 628-643, November.
    3. Chuwen Zhang & Jonathan F. Bard & Rodolfo Chacon, 2017. "Controlling work in process during semiconductor assembly and test operations," International Journal of Production Research, Taylor & Francis Journals, vol. 55(24), pages 7251-7275, December.
    4. Chuang Wang & Pingyu Jiang, 2019. "Deep neural networks based order completion time prediction by using real-time job shop RFID data," Journal of Intelligent Manufacturing, Springer, vol. 30(3), pages 1303-1318, March.
    5. Reha Uzsoy & John W. Fowler & Lars Mönch, 2018. "A survey of semiconductor supply chain models Part II: demand planning, inventory management, and capacity planning," International Journal of Production Research, Taylor & Francis Journals, vol. 56(13), pages 4546-4564, July.
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