Controlling work in process during semiconductor assembly and test operations

This paper introduces a mid-term planning model for scheduling assembly and test operations aimed at minimising the difference between customer demand and product completions each day. A secondary objective is to maximise daily surplus which is a surrogate for throughput. Typically, semiconductor companies have 1000s of products or devices in their catalogue that can be organised into unique groups of up to a 100 devices each. This simplifies the planning process because it is only necessary to consider the groups as a whole rather than the individual devices when constructing schedules. In all, we developed and tested three related models. Each provides daily production rates at each process step for each device group for up to one month at a time. The models are distinguished by how cycle time is treated. The first takes a steady-state approach and uses Little’s Law to formulate a WIP target constraint based on the average cycle time at each processing step. The second and third include integer and fractional cycle times in the variable definitions. To find solutions, raw production data are analysed in a preprocessing step and then converted to input files in a standard format. FlopC++ from the COIN-OR open source software project is used to write and solve the model. Testing was done using three data-sets from the Taiwan AT facility of a global semiconductor firm. By comparing model output with historical data for 6 device groups and 33 process steps, we were able to realise decreases in shortages of up to 40% per month.