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FPGA-Based Implementation of MMC Control Based on Sorting Networks

Author

Listed:
  • Mattia Ricco

    (Department of Energy Technology, Aalborg University, 9100 Aalborg, Denmark)

  • Laszlo Mathe

    (Department of Energy Technology, Aalborg University, 9100 Aalborg, Denmark)

  • Eric Monmasson

    (SATIE lab, Cergy-Pontoise University, 95031 Cergy Pontoise, France)

  • Remus Teodorescu

    (Department of Energy Technology, Aalborg University, 9100 Aalborg, Denmark)

Abstract

In Modular Multilevel Converter (MMC) applications, the balancing of the capacitor voltages is one of the most important issues for achieving the proper behavior of the MMC. The Capacitor Voltage Balancing (CVB) control is usually based on classical sorting algorithms which consist of repetitive/recursive loops. This leads to an increase of the execution time when many Sub-Modules (SMs) are employed. When the execution time of the balancing is longer than the sampling period, the proper operation of the MMC cannot be ensured. Moreover, due to their inherent sequential operation, sorting algorithms are suitable for software implementation (microcontrollers or DSPs), but they are not appropriate for a hardware implementation. Instead, in this paper, Sorting Networks (SNs) are proposed due to their convenience for implementation in FPGA devices. The advantages and the main challenges of the Bitonic SN in MMC applications are discussed and different FPGA implementations are presented. Simulation results are provided in normal and faulty conditions. Moreover, a comparison with the widely used bubble sorting algorithm and max/min approach is made in terms of execution time and performance. Finally, hardware-in-the-loop results are shown to prove the effectiveness of the implemented SN.

Suggested Citation

  • Mattia Ricco & Laszlo Mathe & Eric Monmasson & Remus Teodorescu, 2018. "FPGA-Based Implementation of MMC Control Based on Sorting Networks," Energies, MDPI, vol. 11(9), pages 1-18, September.
    • Handle: RePEc:gam:jeners:v:11:y:2018:i:9:p:2394-:d:169119
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    Citations

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    Cited by:

    1. Xizheng Guo & Jiaqi Yuan & Yiguo Tang & Xiaojie You, 2018. "Hardware in the Loop Real-time Simulation for the Associated Discrete Circuit Modeling Optimization Method of Power Converters," Energies, MDPI, vol. 11(11), pages 1-14, November.
    2. Zhansen Akhmetov & Manel Hammami & Gabriele Grandi & Alex Ruderman, 2019. "On PWM Strategies and Current THD for Single- and Three-Phase Cascade H-Bridge Inverters with Non-Equal DC Sources," Energies, MDPI, vol. 12(3), pages 1-17, January.
    3. Guido Ala & Massimo Caruso & Rosario Miceli & Filippo Pellitteri & Giuseppe Schettino & Marco Trapanese & Fabio Viola, 2019. "Experimental Investigation on the Performances of a Multilevel Inverter Using a Field Programmable Gate Array-Based Control System," Energies, MDPI, vol. 12(6), pages 1-17, March.
    4. Fabio Viola, 2018. "Experimental Evaluation of the Performance of a Three-Phase Five-Level Cascaded H-Bridge Inverter by Means FPGA-Based Control Board for Grid Connected Applications," Energies, MDPI, vol. 11(12), pages 1-47, November.
    5. Xu Tian & Xingcheng Li & Zibo Zhou, 2020. "Novel Uninterruptible Phase-Separation Passing and Power Quality Compensation Scheme Based on Modular Multilevel Converter for Double-Track Electrified Railway," Energies, MDPI, vol. 13(3), pages 1-17, February.
    6. Xu Tian & Yue Ma & Jintao Yu & Cong Wang & Hong Cheng, 2019. "A Modified One-Cycle-Control Method for Modular Multilevel Converters," Energies, MDPI, vol. 12(1), pages 1-17, January.

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