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A planning and scheduling model for onsertion in printed circuit board assembly

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  • Ashayeri, J.
  • Selen, W.

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  • Ashayeri, J. & Selen, W., 2007. "A planning and scheduling model for onsertion in printed circuit board assembly," European Journal of Operational Research, Elsevier, vol. 183(2), pages 909-925, December.
    • Handle: RePEc:eee:ejores:v:183:y:2007:i:2:p:909-925
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    References listed on IDEAS

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    1. BALAKRISHNAN, Anantaram & VANDERBECK, François, 1993. "A Tactical Planning Model for Mixed-Model Electronics Assembly Operations," LIDAM Discussion Papers CORE 1993049, Université catholique de Louvain, Center for Operations Research and Econometrics (CORE).
    2. John D. C. Little & Katta G. Murty & Dura W. Sweeney & Caroline Karel, 1963. "An Algorithm for the Traveling Salesman Problem," Operations Research, INFORMS, vol. 11(6), pages 972-989, December.
    3. Javad Ahmadi & Reza Ahmadi & Hirofumi Matsuo & Devanath Tirupati, 1995. "Component Fixture Positioning/Sequencing for Printed Circuit Board Assembly with Concurrent Operations," Operations Research, INFORMS, vol. 43(3), pages 444-457, June.
    4. Christopher B. Lofgren & Leon F. McGinnis & Craig A. Tovey, 1991. "Routing Printed Circuit Cards Through an Assembly Cell," Operations Research, INFORMS, vol. 39(6), pages 992-1004, December.
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    1. Yazdani Sabouni, M.T. & Logendran, Rasaratnam, 2013. "Carryover sequence-dependent group scheduling with the integration of internal and external setup times," European Journal of Operational Research, Elsevier, vol. 224(1), pages 8-22.

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