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Enhancing the Effectiveness of Cycle Time Estimation in Wafer Fabrication-Efficient Methodology and Managerial Implications

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  • Toly Chen

    (Department of Industrial Engineering and Systems Management, Feng Chia University, 100, Wenhwa Road, Seatwen, Taichung City 407, Taiwan)

  • Yu-Cheng Wang

    (Department of Industrial Engineering and Systems Management, Feng Chia University, 100, Wenhwa Road, Seatwen, Taichung City 407, Taiwan)

Abstract

Cycle time management plays an important role in improving the performance of a wafer fabrication factory. It starts from the estimation of the cycle time of each job in the wafer fabrication factory. Although this topic has been widely investigated, several issues still need to be addressed, such as how to classify jobs suitable for the same estimation mechanism into the same group. In contrast, in most existing methods, jobs are classified according to their attributes. However, the differences between the attributes of two jobs may not be reflected on their cycle times. The bi-objective nature of classification and regression tree (CART) makes it especially suitable for tackling this problem. However, in CART, the cycle times of jobs of a branch are estimated with the same value, which is far from accurate. For these reason, this study proposes a joint use of principal component analysis (PCA), CART, and back propagation network (BPN), in which PCA is applied to construct a series of linear combinations of original variables to form new variables that are as unrelated to each other as possible. According to the new variables, jobs are classified using CART before estimating their cycle times with BPNs. A real case was used to evaluate the effectiveness of the proposed methodology. The experimental results supported the superiority of the proposed methodology over some existing methods. In addition, the managerial implications of the proposed methodology are also discussed with an example.

Suggested Citation

  • Toly Chen & Yu-Cheng Wang, 2014. "Enhancing the Effectiveness of Cycle Time Estimation in Wafer Fabrication-Efficient Methodology and Managerial Implications," Sustainability, MDPI, vol. 6(8), pages 1-22, August.
  • Handle: RePEc:gam:jsusta:v:6:y:2014:i:8:p:5107-5128:d:39047
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    References listed on IDEAS

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    1. Robert C. Leachman & Jeenyoung Kang & Vincent Lin, 2002. "SLIM: Short Cycle Time and Low Inventory in Manufacturing at Samsung Electronics," Interfaces, INFORMS, vol. 32(1), pages 61-77, February.
    2. Toly Chen, 2013. "A Systematic Cycle Time Reduction Procedure for Enhancing the Competitiveness and Sustainability of a Semiconductor Manufacturer," Sustainability, MDPI, vol. 5(11), pages 1-16, November.
    3. Hong Chen & J. Michael Harrison & Avi Mandelbaum & Ann Van Ackere & Lawrence M. Wein, 1988. "Empirical Evaluation of a Queueing Network Model for Semiconductor Wafer Fabrication," Operations Research, INFORMS, vol. 36(2), pages 202-215, April.
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