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Mathematical programming models for scheduling in a CPU/FPGA architecture with heterogeneous communication delays

Author

Listed:
  • Abdessamad Ait El Cadi

    (UVHC - LAMIH CNRS UMR 8201
    IRT Railenium, Espace Technopôle, Le Mont Houy)

  • Omar Souissi

    (UVHC - LAMIH CNRS UMR 8201)

  • Rabie Ben Atitallah

    (UVHC - LAMIH CNRS UMR 8201)

  • Nicolas Belanger

    (Aéroport Marseille Provence)

  • Abdelhakim Artiba

    (UVHC - LAMIH CNRS UMR 8201)

Abstract

This paper deals with the mathematical modelling of a scheduling problem in a heterogeneous CPU/FPGA architecture with heterogeneous communication delays in order to minimize the makespan, $$C_{max}$$ C m a x . This study was motivated by the quality of the available solvers for Mixed Integer Program. The proposed model includes the communication delay constraints in a heterogeneous case, depending on both tasks and computing units. These constraints are linearized without adding any extra variables and the obtained linear model is reduced to speed-up the solving with CPLEX up to 60 times. Computational results show that the proposed model is promising. For an average sized problem of up to 50 tasks and five computing units the solving time under CPLEX is a few seconds.

Suggested Citation

  • Abdessamad Ait El Cadi & Omar Souissi & Rabie Ben Atitallah & Nicolas Belanger & Abdelhakim Artiba, 2018. "Mathematical programming models for scheduling in a CPU/FPGA architecture with heterogeneous communication delays," Journal of Intelligent Manufacturing, Springer, vol. 29(3), pages 629-640, March.
    • Handle: RePEc:spr:joinma:v:29:y:2018:i:3:d:10.1007_s10845-015-1075-z
    DOI: 10.1007/s10845-015-1075-z
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    References listed on IDEAS

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    1. S. Zhang & T. N. Wong, 2018. "Integrated process planning and scheduling: an enhanced ant colony optimization heuristic with parameter tuning," Journal of Intelligent Manufacturing, Springer, vol. 29(3), pages 585-601, March.
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    3. SOUSA, Jorge P. & WOLSEY, Laurence A., 1992. "A time indexed formulation of non-preemptive single machine scheduling problems," LIDAM Reprints CORE 984, Université catholique de Louvain, Center for Operations Research and Econometrics (CORE).
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