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A hardware approach to value function iteration

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  • Peri, Alessandro

Abstract

This paper proposes a novel approach for the computation of dynamic stochastic equilibrium models. We design an FPGA specialized in the computation of a Bellman equation via value function iteration (VFI). Our hardware approach exhibits significant speed gains vis-à-vis GPU-based data-parallelization techniques. The speed gains arise from two layers of parallelism, accessible to hardware developers: instruction-level and pipeline parallelism at the logical resources level. By and large, the paper documents significant computational speed gains from hardware specialization, so far unexplored by the macroeconomic literature.

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  • Peri, Alessandro, 2020. "A hardware approach to value function iteration," Journal of Economic Dynamics and Control, Elsevier, vol. 114(C).
    • Handle: RePEc:eee:dyncon:v:114:y:2020:i:c:s0165188920300622
    DOI: 10.1016/j.jedc.2020.103894
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    References listed on IDEAS

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    7. Aldrich, Eric M. & Fernández-Villaverde, Jesús & Ronald Gallant, A. & Rubio-Ramírez, Juan F., 2011. "Tapping the supercomputer under your desk: Solving dynamic equilibrium models with graphics processors," Journal of Economic Dynamics and Control, Elsevier, vol. 35(3), pages 386-393, March.
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    Cited by:

    1. Jesus Fernandez-Villaverde & Pablo Guerron-Quintana, 2020. "Uncertainty Shocks and Business Cycle Research," Review of Economic Dynamics, Elsevier for the Society for Economic Dynamics, vol. 37, pages 118-166, August.

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    More about this item

    Keywords

    FPGA; Dynamic programming; Pipelining; Growth model; Business cycles;
    All these keywords.

    JEL classification:

    • C88 - Mathematical and Quantitative Methods - - Data Collection and Data Estimation Methodology; Computer Programs - - - Other Computer Software

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