IC Yeld Analysis: an innovative approach for clustering wafer/chip electrical failures

Yeld analysis is an activity common to all companies manufacturing semiconductor devices on an industrial scale and consists in identifying problems relating to the production cycle by analyzing the number and distribution of non-functioning chips on the wafer. This is an extremely expensive activity from the point of view of human resources employed because it requires the visual analysis of thousands of maps (graphical representations of the distribution of non-functioning chips) on silicon wafers produced and analyzing a huge amount of (not only) electrical related data. On the other hand, yeld (percentage of chips running on a wafer) analysis is absolutely essential, because it is linked directly to the marketing and the potential profit margin of produced devices. Schematically, this activity can lead to a problem of recognition of models (known issues, typically dealt with supervised neural networks) in a high noise environment, or how to bind the data to different wafers based on models that are not known a priori (search for unknown problems, or clustering, dealt with appropriate algorithms and/or with unsupervised neural networks). In this work we analyze the general problems of locating the most significant yeld issues and then evaluate the applicability of neural network in combination with appropriate clustering algorithms, with the attempt to emerge, and possibly solve the problems inherent yeld management, especially in environments with high volumes of production.