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Experience With The Ibm Zisc036 Neural Network Chip

Author

Listed:
  • CLARK S. LINDSEY

    (Physics Dept. (Frescati), Royal Institute of Technology, Frescativägen 24, 104 05 Stockholm, Sweden)

  • THOMAS LINDBLAD

    (Physics Dept. (Frescati), Royal Institute of Technology, Frescativägen 24, 104 05 Stockholm, Sweden)

  • GIVI SEKHNIAIDZE

    (Physics Dept. (Frescati), Royal Institute of Technology, Frescativägen 24, 104 05 Stockholm, Sweden)

  • G. SZÉKELY

    (Physics Dept. (Frescati), Royal Institute of Technology, Frescativägen 24, 104 05 Stockholm, Sweden)

  • M. MINERSKJÖLD

    (Physics Dept. (Frescati), Royal Institute of Technology, Frescativägen 24, 104 05 Stockholm, Sweden)

Abstract

The new IBM Zero Instruction Set Computer (ZISC) provides a radial basis function neural network. The first generation chip (ZISC036) allows for 64 8-bit inputs, 36 RBF neurons in the middle layer, and up to 16383 possible output categories. Forward processing takes 4μs with a 20MHz clock. Cascading multiple chips increases the number of available RBF’s with no increase in processing time. The chip also executes a learning algorithm. We report on tests of the ZISC with a high energy physics related task.

Suggested Citation

  • Clark S. Lindsey & Thomas Lindblad & Givi Sekhniaidze & G. Székely & M. Minerskjöld, 1995. "Experience With The Ibm Zisc036 Neural Network Chip," International Journal of Modern Physics C (IJMPC), World Scientific Publishing Co. Pte. Ltd., vol. 6(04), pages 579-584.
    • Handle: RePEc:wsi:ijmpcx:v:06:y:1995:i:04:n:s0129183195000460
    DOI: 10.1142/S0129183195000460
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