Rapid multi-objective design of integrated on-chip inductors by means of Pareto front exploration and design extrapolation

Identification of the best trade-offs between conflicting design objectives allows for making educated design decisions as well as assessing suitability of a given component or circuit for a specific application. In case of inductors, the typical objectives include maximization of the quality factor and minimization of the layout area, as well as maintaining a required inductance at a given operating frequency. This work demonstrates low-cost multi-objective design optimization of integrated inductors. The primary technique utilized here is a point-by-point Pareto front exploration where subsequent Pareto-optimal designs are obtained by moving along the front using local search methods. Considerable reduction of the design cost is achieved by extrapolating inductor dimensions at the subsequent optimal point, based on already available data as well as size constraints. The proposed methodology is verified using two examples of spiral inductors implemented in 65-nm CMOS technology. Comparisons with point-by-point optimization without extrapolation are also provided.