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Design and verification of improved CMERE against power analysis attacks

Author

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  • Hridoy Jyoti Mahanta
  • Abhilash Chakraborty
  • Ajoy Kumar Khan

Abstract

The CMERE algorithm was designed to resist DPA attacks on modular exponentiation. It was implemented and tested at the algorithmic level for different key sizes of the RSA cryptosystems. The strength of CMERE lied on the facts that it could be implemented both on left-to-right and right-to-left binary methods for modular exponentiation without any changes in the original algorithm. Also, the execution of modular exponentiation was completely bit independent making it a very strong countermeasure against simple and differential power analysis attacks. In this paper, we have verified the CMERE algorithm at hardware level using VHDL. During formal verification with VHDL on FPGA, the algorithm was modified for practical implementation. However, the overall strength of the improved CMERE algorithm remains the same as the original algorithm.

Suggested Citation

  • Hridoy Jyoti Mahanta & Abhilash Chakraborty & Ajoy Kumar Khan, 2020. "Design and verification of improved CMERE against power analysis attacks," Cyber-Physical Systems, Taylor & Francis Journals, vol. 6(3), pages 165-179, July.
    • Handle: RePEc:taf:tcybxx:v:6:y:2020:i:3:p:165-179
    DOI: 10.1080/23335777.2020.1769735
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