Design and analysis of a novel compact quaternary adder

Short channel effects, where the channel length is equivalent to the source and drain junction depletion layer thicknesses, are becoming more prevalent. The need for alternative technologies has grown significantly due to these consequences; in scaled CMOS circuits, Drain-induced barrier lowering, velocity saturation, quantum confinement, and hot carrier degradation are examples of these effects. Furthermore, the limited area required through interconnections and the scaling effort to build more efficient and denser circuits has been hampered by the increased power density in nanoscale binary circuits. As a result, building effective nanoscale multiple-valued circuits is critical. This work proposes a low-power, small-area quaternary adder based on CNTFET switching logic. The proposed design reduces the number of transistors, size, and power consumption while maintaining full-swing operation and output driving capabilities. The Stanford Virtual-Source Carbon Nanotube Field Effect Transistor Model version 1.01 simulates the recommended design using sub-15 nm CNFET technology. Binary logic has become extremely difficult as the VLSI industry progresses. Adder logic, such as ternary and Quaternary adder logic, are examples of MVL, a multi-valued logic utilized to address this difficulty. Quaternary logic has four inputs: 0, 1, 2, 3, and so on 0, 0.2, 0.4, and 0.6 are the values for these inputs. Regarding chip size and interconnection complexity, MVL designs outperform binary logic architectures. To ensure this promising proposed design works appropriately, voltage dividers are used to construct basic gates, half-adders, and full-adders.