High speed and area efficient coded input BCSM shared LUT-based FIR filter architecture

Recent advancements in communication technologies demand optimal filter design for the relevant application. This work proposes an efficient lookup table (LUT) based pipelined reconfigurable finite impulse response filter (FIR) architecture. This LUT utilized FIR filter structure is implemented with various filter orders. The proposed LUT approach comprises effective coding of input as well as sharing of common binary terms that is sharing of binary common subexpression multiplication (BCSM) terms which are used to curtail the number of memory positions which brings out lower area occupancy. Further, the availability of multiplied terms in LUT enhances the speed of operation to a significant extent. The proposed filter with a LUT-based inner product generation scheme achieves good performance in terms of delay, area, and power. The proposed filter architecture is implemented in Xilinx and Altera—FPGA platforms using hybrid parameterizable Verilog cores. The performance parameters such as slice count, maximum frequency, and delay for different orders as well as different address lengths are considered for the analysis of the proposed architecture. The proposed filter structure achieves speed improvement and minimized area when examined with the existing FIR Filter architectures. The suggested filter architecture provides a maximum frequency of operation of 400 MHz as well as an 80% reduction in the area over the conventional architectures.