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Design and performance analysis of low power and energy-efficient vedic multipliers

Author

Listed:
  • Sadulla Shaik

    (KKR and KSR Institute of Technology and Sciences)

  • Satish Kanapala

    (Vignan’s Foundation for Science Technology and Research)

  • Vallabhuni Vijay

    (Department of Electronics and Communication Engineering, Institute of Aeronautical Engineering)

  • Chandra Shaker Pittala

    (MLR Institute of Technology)

Abstract

This paper explores low-power and energy-efficient multi-bit Vedic Multiplier (VM) architectures at a supply voltage as low as 0.6 V. Energy efficient architectures are a significant concern in VLSI, the Internet of Things (IoT), wireless communications, cryptographic algorithms, and Digital Signal Processing (DSP) circuits. The proposed multipliers are designed with a Vedic multiplication algorithm using the Vedic mathematics formula Urdhva Tiryakbhyam (UT) method. This paper provides design insights and a circuit interaction approach with complementary Metal Oxide Semiconductor (CMOS) and FinFET technologies for designing VM blocks. All the proposed designs show better power delay product (PDP) characteristics at VDD 0.6 V. FinFET-based 8-bit VM design has lower power consumption and PDP of 36.5% and 55.8%, respectively, compared with CMOS 8-bit VM design at a supply voltage of 0.6 V.

Suggested Citation

  • Sadulla Shaik & Satish Kanapala & Vallabhuni Vijay & Chandra Shaker Pittala, 2023. "Design and performance analysis of low power and energy-efficient vedic multipliers," International Journal of System Assurance Engineering and Management, Springer;The Society for Reliability, Engineering Quality and Operations Management (SREQOM),India, and Division of Operation and Maintenance, Lulea University of Technology, Sweden, vol. 14(3), pages 894-902, June.
    • Handle: RePEc:spr:ijsaem:v:14:y:2023:i:3:d:10.1007_s13198-023-01889-1
    DOI: 10.1007/s13198-023-01889-1
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    References listed on IDEAS

    as
    1. Vallabhuni Vijay & C. V. Sai Kumar Reddy & Chandra Shaker Pittala & Rajeev Ratna Vallabhuni & M. Saritha & M. Lavanya & S. China Venkateswarlu & M. Sreevani, 2021. "ECG performance validation using operational transconductance amplifier with bias current," International Journal of System Assurance Engineering and Management, Springer;The Society for Reliability, Engineering Quality and Operations Management (SREQOM),India, and Division of Operation and Maintenance, Lulea University of Technology, Sweden, vol. 12(6), pages 1173-1179, December.
    2. Kancharapu Chaitanya & Mohammad Khadir & S. Sushma & Lavanya Nalla & G. Naveen & N. Manjula & M. Saritha & M. Lavanya & Mulinti Narendra Reddy & Vallabhuni Vijay, 2022. "Double-threshold energy detection: noisy environment applied cognitive radio," International Journal of System Assurance Engineering and Management, Springer;The Society for Reliability, Engineering Quality and Operations Management (SREQOM),India, and Division of Operation and Maintenance, Lulea University of Technology, Sweden, vol. 13(6), pages 2944-2948, December.
    3. S. Swathi & S. Sushma & C. Devi Supraja & V. Bindusree & L. Babitha & Vallabhuni Vijay, 2022. "A hierarchical image matting model for blood vessel segmentation in retinal images," International Journal of System Assurance Engineering and Management, Springer;The Society for Reliability, Engineering Quality and Operations Management (SREQOM),India, and Division of Operation and Maintenance, Lulea University of Technology, Sweden, vol. 13(3), pages 1093-1101, June.
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