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Performance improvement and analysis of snoopy cache coherence based multicore architectures

Author

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  • Amit D. Joshi

    (National Institute of Technology)

  • N. Ramasubramanian

    (National Institute of Technology)

Abstract

Multicore architectures are being used in different sectors like automobile, avionics, and health-care. Correctness of shared data is the most important concern in multicore architectures. Sharing of data yields problem of cache coherence with inconsistent memory state that affects system performance. Conventional cache coherence protocols are not predictable in nature. Predictable Modified-Shared-Invalid method addressed the issue of unpredictability. This work proposes a slot stealing approach to interconnection bus with change in slot width. The predictability is applied to the Modified-Exclusive-Shared-Invalid variant of snoopy bus protocol with the proposed slot stealing approach. Implementation shows that the worst case latencies are reduced and following the analytical bound. Experimental results show the reduced execution time and energy in the configurations with 32 KB all set associative schemes compared with Predictable Modified-Shared-Invalid. The relative reductions in execution time and total energy are observed in the different configurations. The proposed slot stealing approach with Predictable Modified-Exclusive-Shared-Invalid protocol has reduced the worst case latencies, execution time, and energy consumption.

Suggested Citation

  • Amit D. Joshi & N. Ramasubramanian, 2023. "Performance improvement and analysis of snoopy cache coherence based multicore architectures," International Journal of System Assurance Engineering and Management, Springer;The Society for Reliability, Engineering Quality and Operations Management (SREQOM),India, and Division of Operation and Maintenance, Lulea University of Technology, Sweden, vol. 14(3), pages 848-864, July.
    • Handle: RePEc:spr:ijsaem:v:14:y:2023:i:3:d:10.1007_s13198-021-01177-w
    DOI: 10.1007/s13198-021-01177-w
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