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Hardware Architecture for Real-Time Computation of Image Component Feature Descriptors on a FPGA

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  • Abdul Waheed Malik
  • Benny Thörnberg
  • Muhammad Imran
  • Najeem Lawal

Abstract

This paper describes a hardware architecture for real-time image component labeling and the computation of image component feature descriptors. These descriptors are object related properties used to describe each image component. Embedded machine vision systems demand a robust performance and power efficiency as well as minimum area utilization, depending on the deployed application. In the proposed architecture, the hardware modules for component labeling and feature calculation run in parallel. A CMOS image sensor (MT9V032), operating at a maximum clock frequency of 27 MHz, was used to capture the images. The architecture was synthesized and implemented on a Xilinx Spartan-6 FPGA. The developed architecture is capable of processing 390 video frames per second of size 640 × 480 pixels. Dynamic power consumption is 13 mW at 86 frames per second.

Suggested Citation

  • Abdul Waheed Malik & Benny Thörnberg & Muhammad Imran & Najeem Lawal, 2014. "Hardware Architecture for Real-Time Computation of Image Component Feature Descriptors on a FPGA," International Journal of Distributed Sensor Networks, , vol. 10(1), pages 815378-8153, January.
    • Handle: RePEc:sae:intdis:v:10:y:2014:i:1:p:815378
    DOI: 10.1155/2014/815378
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