Author
Listed:
- Anna Goldie
(Google Research, Brain Team, Google
Stanford University)
- Azalia Mirhoseini
(Google Research, Brain Team, Google
Stanford University)
- Mustafa Yazgan
(Google Chip Implementation and Infrastructure (CI2) Team, Google)
- Joe Wenjie Jiang
(Google Research, Brain Team, Google)
- Ebrahim Songhori
(Google Research, Brain Team, Google)
- Shen Wang
(Google Research, Brain Team, Google)
- Young-Joon Lee
(Google Chip Implementation and Infrastructure (CI2) Team, Google)
- Eric Johnson
(Google Research, Brain Team, Google)
- Omkar Pathak
(Google Chip Implementation and Infrastructure (CI2) Team, Google)
- Azade Nova
(Google Research, Brain Team, Google)
- Jiwoo Pak
(Google Chip Implementation and Infrastructure (CI2) Team, Google)
- Andy Tong
(Google Chip Implementation and Infrastructure (CI2) Team, Google)
- Kavya Srinivasa
(Google Chip Implementation and Infrastructure (CI2) Team, Google)
- William Hang
(Stanford University)
- Emre Tuncer
(Google Chip Implementation and Infrastructure (CI2) Team, Google)
- Quoc V. Le
(Google Research, Brain Team, Google)
- James Laudon
(Google Research, Brain Team, Google)
- Richard Ho
(Google Chip Implementation and Infrastructure (CI2) Team, Google)
- Roger Carpenter
(Google Chip Implementation and Infrastructure (CI2) Team, Google)
- Jeff Dean
(Google Research, Brain Team, Google)
Abstract
No abstract is available for this item.
Suggested Citation
Anna Goldie & Azalia Mirhoseini & Mustafa Yazgan & Joe Wenjie Jiang & Ebrahim Songhori & Shen Wang & Young-Joon Lee & Eric Johnson & Omkar Pathak & Azade Nova & Jiwoo Pak & Andy Tong & Kavya Srinivasa, 2024.
"Addendum: A graph placement methodology for fast chip design,"
Nature, Nature, vol. 634(8034), pages 10-11, October.
Handle:
RePEc:nat:nature:v:634:y:2024:i:8034:d:10.1038_s41586-024-08032-5
DOI: 10.1038/s41586-024-08032-5
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