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Highly stacked 3D organic integrated circuits with via-hole-less multilevel metal interconnects

Author

Listed:
  • Hocheon Yoo

    (Pohang University of Science and Technology (POSTECH))

  • Hongkeun Park

    (Korea Advanced Institute of Science and Technology (KAIST))

  • Seunghyun Yoo

    (Pohang University of Science and Technology (POSTECH))

  • Sungmin On

    (Pohang University of Science and Technology (POSTECH))

  • Hyejeong Seong

    (Imperial College London)

  • Sung Gap Im

    (Korea Advanced Institute of Science and Technology (KAIST))

  • Jae-Joon Kim

    (Pohang University of Science and Technology (POSTECH))

Abstract

Multilevel metal interconnects are crucial for the development of large-scale organic integrated circuits. In particular, three-dimensional integrated circuits require a large number of vertical interconnects between layers. Here, we present a novel multilevel metal interconnect scheme that involves solvent-free patterning of insulator layers to form an interconnecting area that ensures a reliable electrical connection between two metals in different layers. Using a highly reliable interconnect method, the highest stacked organic transistors to date, a three-dimensional organic integrated circuits consisting of 5 transistors and 20 metal layers, is successfully fabricated in a solvent-free manner. All transistors exhibit outstanding device characteristics, including a high on/off current ratio of ~107, no hysteresis behavior, and excellent device-to-device uniformity. We also demonstrate two vertically-stacked complementary inverter circuits that use transistors on 4 different floors. All circuits show superb inverter characteristics with a 100% output voltage swing and gain up to 35 V per V.

Suggested Citation

  • Hocheon Yoo & Hongkeun Park & Seunghyun Yoo & Sungmin On & Hyejeong Seong & Sung Gap Im & Jae-Joon Kim, 2019. "Highly stacked 3D organic integrated circuits with via-hole-less multilevel metal interconnects," Nature Communications, Nature, vol. 10(1), pages 1-9, December.
  • Handle: RePEc:nat:natcom:v:10:y:2019:i:1:d:10.1038_s41467-019-10412-9
    DOI: 10.1038/s41467-019-10412-9
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    Cited by:

    1. Junhwan Choi & Changhyeon Lee & Chungryeol Lee & Hongkeun Park & Seung Min Lee & Chang-Hyun Kim & Hocheon Yoo & Sung Gap Im, 2022. "Vertically stacked, low-voltage organic ternary logic circuits including nonvolatile floating-gate memory transistors," Nature Communications, Nature, vol. 13(1), pages 1-10, December.

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