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OR Practice—Lagrangian Relaxation for Testing Infeasibility in VLSI Routing

Author

Listed:
  • Thomas A. Feo

    (University of California, Berkeley, California)

  • Dorit S. Hochbaum

    (University of California, Berkeley, California)

Abstract

We present a technique for very large scale integrated (VLSI) circuit design that recognizes the infeasibility of connecting pairs of terminals on modules placed on a chip. The method is based on a novel application of Lagrangian relaxation. Positive empirical results obtained from difficult problems found both in the literature and in industry strongly support the usefulness of this method. It has been incorporated in the proprietary computer-aided integrated circuit design package used at Bell Communications Research Inc., that allows systems engineers to design integrated circuits independent of the manufacturing processes specified by the foundries making the chips. The method has resulted in a faster turnaround time in the Bell design process.

Suggested Citation

  • Thomas A. Feo & Dorit S. Hochbaum, 1986. "OR Practice—Lagrangian Relaxation for Testing Infeasibility in VLSI Routing," Operations Research, INFORMS, vol. 34(6), pages 819-831, December.
    • Handle: RePEc:inm:oropre:v:34:y:1986:i:6:p:819-831
    DOI: 10.1287/opre.34.6.819
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