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FPGA Implementation of Fast and Efficient CODEC for H.264/AVC Real Time Video Applications

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  • Yasser Ismail

    (Department of Computer Engineering, University of Bahrain, Sakhair, Bahrain)

Abstract

Low power networks are considered nowadays as a fundamental environment for connecting and communicating various “things.” Such connected things form the hot topic Internet-of-Things (IoT) that emphasizes on better and smarter interconnected world. The two main important issues raised in the IoT are the transmitted bit-rate and the device processing capability limitations. In this paper, a smart Skipping Motion Estimation threshold (TSME) is implemented and elaborated to match the processing capabilities of the IoT devices. The proposed threshold aims to achieve a great reduction in the computations of the Motion Estimation (ME) process with acceptable bit-rate and high speed that are suitable for real time video applications. Simulation results show that there is great reductions in the computations represented by the Motion Estimation Time Saving percentage (METS%) up to 51% and 49% in case of using average and median functions, respectively. Implementation results of the proposed threshold unit on an FPGA show low cost hardware with a maximum hardware frequency of 379.140MHz.

Suggested Citation

  • Yasser Ismail, 2016. "FPGA Implementation of Fast and Efficient CODEC for H.264/AVC Real Time Video Applications," International Journal of Technology Diffusion (IJTD), IGI Global, vol. 7(1), pages 32-52, January.
    • Handle: RePEc:igg:jtd000:v:7:y:2016:i:1:p:32-52
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