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Performance Evaluation of SHA-3 Final Round Candidate Algorithms on ARM Cortex–M4 Processor

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  • Rajeev Sobti

    (Lovely Professional University, Punjab, India)

  • Geetha Ganesan

    (Lovely Professional University, Punjab, India)

Abstract

SHA-3 was an open competition initiated by NIST to design new generation of hash functions. This competition was a necessity to overcome the challenges imposed by multiple attacks on MDx family of hash functions including SHA-0 and SHA-1. For this competition, NIST announced a reference platform which did not cover Embedded and Mobile machines. This paper compares the performance of SHA-3 final round candidate algorithms on ARM Cortex-M4 processor (embedded processor) and presents the results. Cycles per Byte is used as performance metric. Cortex-M4 based Stellaris® LM4F232 Evaluation Board (EK-LM4F232) from Texas Instruments is used for performance evaluation.

Suggested Citation

  • Rajeev Sobti & Geetha Ganesan, 2018. "Performance Evaluation of SHA-3 Final Round Candidate Algorithms on ARM Cortex–M4 Processor," International Journal of Information Security and Privacy (IJISP), IGI Global, vol. 12(1), pages 63-73, January.
    • Handle: RePEc:igg:jisp00:v:12:y:2018:i:1:p:63-73
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