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Comparative analysis of different Vedic algorithms for 8 × 8 binary multipliers

Author

Listed:
  • Anu Mehra
  • Vinay Verma
  • Rana Majumdar
  • Nidhi Gaur
  • Alok Kumar
  • Ansh Awasthi
  • Chanda Pandey

Abstract

Multipliers are the basic building blocks of various processors; arithmetic and logical unit and they are widely used in digital signal processing and image processing applications such as convolution, DWT, DCT. In this paper, four separate algorithms for designing binary multipliers are adopted from the ancient Indian Book of Wisdom Sthapatya-veda (an Upa-veda of Atharvaveda). The current work mainly focuses on comparing the power, delay, look up table (LUT), noise margin of different multiplier algorithms using various sutra's of Vedic mathematics which has been implemented on Virtex 7 Board 1.1, using Xilinx Vivado version 14.2.

Suggested Citation

  • Anu Mehra & Vinay Verma & Rana Majumdar & Nidhi Gaur & Alok Kumar & Ansh Awasthi & Chanda Pandey, 2019. "Comparative analysis of different Vedic algorithms for 8 × 8 binary multipliers," International Journal of Industrial and Systems Engineering, Inderscience Enterprises Ltd, vol. 33(2), pages 129-140.
    • Handle: RePEc:ids:ijisen:v:33:y:2019:i:2:p:129-140
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