FPGA Delay-Oriented Process Mapping Algorithm of Xiangxi Minority Based on LUT

At present, FPGA (field-programmable gate array) architecture has made great progress in the requirements of hardware volume, which can meet common needs. However, for the increasing number of resources, it is difficult to significantly reduce the delay of process mapping. Therefore, this paper proposes FDMAP (fit descending map) algorithm from the perspective of the LUT number to reduce the delay. This paper proposes a method of FPGA mapping and debugging for heterogeneous multicore high-performance processors based on isomorphic symmetric FPGA architecture, which effectively utilizes the architectural features of heterogeneous multicore processors and the symmetric features of isomorphic FPGA, divides FPGA functions from top to bottom in a hierarchical way, and constructs FPGA architecture from bottom to top. Using differential bridge and adaptive delay adjustment sampling technology, combined with the embedded virtual logic analyzer debugging tool, FPGA architecture can be lightened and deployed quickly. Multicore complementary core-to-core replacement simulation mapping methods such as debug shells can be used to effectively complete the mapping of the target’s high-performance heterogeneous multicore processor to the entire SOC (system on-ship) chip system-level FPGA. In the aspect of algorithm, the fdmap algorithm is mainly implemented, and the low latency mapping of resources is realized with FPGA architecture. In order to verify the effectiveness of mapping the fdmap algorithm, this paper compares the fdmap algorithm with the vector VM algorithm. The research shows that when the wavelength resolution is 7 pm and the temperature error is less than 1°C, the shell is debugged, and 10 mapping examples are simulated with the fdmap algorithm. In the experiment, the LUT with the most critical 20% is selected, and the closed value of the LUT search type is set to 0.86. Compared with the original data, the number of LUTs increased by 15.2%, and the criticality decreased by 35.21%. Compared with the vector VM algorithm with the biggest gap, the number of LUTs decreased by 14.25%, the criticality improved by 14.21%, and the overall delay decreased by 65%. Therefore, the isomorphic symmetric FPGA architecture proposed in this paper can improve the structural criticality and significantly reduce the latency while reducing the number of LUTs.