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FPGA-Oriented LDPC Decoder for Cyber-Physical Systems

Author

Listed:
  • Mateusz Kuc

    (Institute of Electronics, Silesian University of Technology, ul. Akademicka 2A, 44-100 Gliwice, Poland)

  • Wojciech Sułek

    (Institute of Electronics, Silesian University of Technology, ul. Akademicka 2A, 44-100 Gliwice, Poland)

  • Dariusz Kania

    (Institute of Electronics, Silesian University of Technology, ul. Akademicka 2A, 44-100 Gliwice, Poland)

Abstract

A potentially useful Cyber-Physical Systems element is a modern forward error correction (FEC) coding system, utilizing a code selected from the broad class of Low-Density Parity-Check (LDPC) codes. In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (QC-LDPC) subclass of codes is presented. The decoder can be configured to support the typical decoding algorithms: Min-Sum or Normalized Min-Sum (NMS). A novel method of normalization in the NMS algorithm is proposed, one that utilizes combinational logic instead of arithmetic units. A comparison of decoders with different bit-lengths of data (beliefs that are messages propagated between computing units) is also provided. The presented decoder has been implemented with a distributed control system. Experimental studies were conducted using the Intel Cyclone V FPGA module, which is a part of the developed testing environment for LDPC coding systems.

Suggested Citation

  • Mateusz Kuc & Wojciech Sułek & Dariusz Kania, 2020. "FPGA-Oriented LDPC Decoder for Cyber-Physical Systems," Mathematics, MDPI, vol. 8(5), pages 1-15, May.
    • Handle: RePEc:gam:jmathe:v:8:y:2020:i:5:p:723-:d:353899
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