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New High-Speed Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request Implemented in a Low-Area FPGA

Author

Listed:
  • José Rangel

    (Instituto Politécnico Nacional, ESIME Culhuacan, Av. Santa Ana No. 1000, Ciudad de México 04260, Mexico)

  • Esteban Anides

    (Instituto Politécnico Nacional, ESIME Culhuacan, Av. Santa Ana No. 1000, Ciudad de México 04260, Mexico)

  • Eduardo Vázquez

    (Instituto Politécnico Nacional, ESIME Culhuacan, Av. Santa Ana No. 1000, Ciudad de México 04260, Mexico)

  • Giovanny Sanchez

    (Instituto Politécnico Nacional, ESIME Culhuacan, Av. Santa Ana No. 1000, Ciudad de México 04260, Mexico)

  • Juan-Gerardo Avalos

    (Instituto Politécnico Nacional, ESIME Culhuacan, Av. Santa Ana No. 1000, Ciudad de México 04260, Mexico)

  • Gonzalo Duchen

    (Instituto Politécnico Nacional, ESIME Culhuacan, Av. Santa Ana No. 1000, Ciudad de México 04260, Mexico)

  • Linda K. Toscano

    (Instituto Politécnico Nacional, ESIME Culhuacan, Av. Santa Ana No. 1000, Ciudad de México 04260, Mexico)

Abstract

During the last years, the demand for internet-of-things (IoT) resource-constrained devices has grown exponentially. To address this need, several digital methods have been proposed to improve these devices in terms of area and power consumption. Despite achieving significant results, improvement in these factors is still a challenging task. Recently, an emerging computational area has been seen as a potential solution to improving the performance of conventional binary circuits. In particular, this area uses a method based on spiking neural P systems (SN P) to create arithmetic circuits, such as adders, subtractors, multipliers, and divisors, since these components are vital in many IoT applications. To date, several efforts have been dedicated to decreasing the number of neurons and synapses to create compact circuits. However, processing speed is a persistent issue. In this work, we propose four compact arithmetic circuits with high processing speeds. To evaluate their performance, we designed a neuromorphic processor that is capable of performing four operations using dynamic connectivity. As a consequence, the proposed neuromorphic processor achieves higher processing speeds by maintaining low area consumption in comparison with the existing approaches.

Suggested Citation

  • José Rangel & Esteban Anides & Eduardo Vázquez & Giovanny Sanchez & Juan-Gerardo Avalos & Gonzalo Duchen & Linda K. Toscano, 2024. "New High-Speed Arithmetic Circuits Based on Spiking Neural P Systems with Communication on Request Implemented in a Low-Area FPGA," Mathematics, MDPI, vol. 12(22), pages 1-10, November.
  • Handle: RePEc:gam:jmathe:v:12:y:2024:i:22:p:3472-:d:1515608
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    References listed on IDEAS

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    1. Eduardo Pichardo & Esteban Anides & Angel Vazquez & Luis Garcia & Juan G. Avalos & Giovanny Sánchez & Héctor M. Pérez & Juan C. Sánchez, 2023. "A Compact and High-Performance Acoustic Echo Canceller Neural Processor Using Grey Wolf Optimizer along with Least Mean Square Algorithms," Mathematics, MDPI, vol. 11(6), pages 1-24, March.
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