Author
Listed:
- Royce R. Ramirez-Morales
(Instituto Politécnico Nacional, Centro de Investigación en Computación, Av. Juan de Dios Bátiz s/n, Alcaldía GAM, Ciudad de México 07700, Mexico)
- Victor H. Ponce-Ponce
(Instituto Politécnico Nacional, Centro de Investigación en Computación, Av. Juan de Dios Bátiz s/n, Alcaldía GAM, Ciudad de México 07700, Mexico)
- Herón Molina-Lozano
(Instituto Politécnico Nacional, Centro de Investigación en Computación, Av. Juan de Dios Bátiz s/n, Alcaldía GAM, Ciudad de México 07700, Mexico)
- Humberto Sossa-Azuela
(Instituto Politécnico Nacional, Centro de Investigación en Computación, Av. Juan de Dios Bátiz s/n, Alcaldía GAM, Ciudad de México 07700, Mexico)
- Oscar Islas-García
(Instituto Politécnico Nacional, Centro de Investigación en Computación, Av. Juan de Dios Bátiz s/n, Alcaldía GAM, Ciudad de México 07700, Mexico)
- Elsa Rubio-Espino
(Instituto Politécnico Nacional, Centro de Investigación en Computación, Av. Juan de Dios Bátiz s/n, Alcaldía GAM, Ciudad de México 07700, Mexico)
Abstract
Analog neuromorphic prototyping is essential for designing and testing spiking neuron models that use memristive devices as synapses. These prototypes can have various circuit configurations, implying different response behaviors that custom silicon designs lack. The prototype’s behavior results can be optimized for a specific foundry node, which can be used to produce a customized on-chip parallel deep neural network. Spiking neurons mimic how the biological neurons in the brain communicate through electrical potentials. Doing so enables more powerful and efficient functionality than traditional artificial neural networks that run on von Neumann computers or graphic processing unit-based platforms. Therefore, on-chip parallel deep neural network technology can accelerate deep learning processing, aiming to exploit the brain’s unique features of asynchronous and event-driven processing by leveraging the neuromorphic hardware’s inherent parallelism and analog computation capabilities. This paper presents the design and implementation of a leaky integrate-and-fire (LIF) neuron prototype implemented with commercially available components on a PCB board. The simulations conducted in LTSpice agree well with the electrical test measurements. The results demonstrate that this design can be used to interconnect many boards to build layers of physical spiking neurons, with spike-timing-dependent plasticity as the primary learning algorithm, contributing to the realization of experiments in the early stage of adopting analog neuromorphic computing.
Suggested Citation
Royce R. Ramirez-Morales & Victor H. Ponce-Ponce & Herón Molina-Lozano & Humberto Sossa-Azuela & Oscar Islas-García & Elsa Rubio-Espino, 2024.
"Analog Implementation of a Spiking Neuron with Memristive Synapses for Deep Learning Processing,"
Mathematics, MDPI, vol. 12(13), pages 1-25, June.
Handle:
RePEc:gam:jmathe:v:12:y:2024:i:13:p:2025-:d:1425482
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