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Efficient Implementation of SPEEDY Block Cipher on Cortex-M3 and RISC-V Microcontrollers

Author

Listed:
  • Hyunjun Kim

    (Division of IT Convergence Engineering, Hansung University, Seoul 02876, Korea)

  • Siwoo Eum

    (Division of IT Convergence Engineering, Hansung University, Seoul 02876, Korea)

  • Minjoo Sim

    (Division of IT Convergence Engineering, Hansung University, Seoul 02876, Korea)

  • Hwajeong Seo

    (Division of IT Convergence Engineering, Hansung University, Seoul 02876, Korea)

Abstract

The SPEEDY block cipher family announced at the CHES 2021 shows excellent performance on hardware architectures. Due to the nature of the hardware-friendly design of SPEEDY, the algorithm has low performance for software implementations. In particular, 6-bit S-box and bit permutation operations of SPEEDY are inefficient in software implementations, where it performs word-wise computations. We implemented the SPEEDY block cipher on a 32-bit microcontroller for the first time by applying the bit-slicing techniques. The optimized encryption performance results on ARM Cortex-M3 for SPEEDY-5-192, SPEEDY-6-192, and SPEEDY-7-192 are 65.7, 75.25, and 85.16 clock cycles per byte (i.e., cpb), respectively. It showed better performance than AES-128 constant-time implementation and GIFT constant-time implementation in the same platform. In RISC-V, the performance showed 81.9, 95.5, and 109.2 clock cycles per byte, which outperformed the previous works. Finally, we conclude that SPEEDY can show efficient software implementation on low-end embedded environments.

Suggested Citation

  • Hyunjun Kim & Siwoo Eum & Minjoo Sim & Hwajeong Seo, 2022. "Efficient Implementation of SPEEDY Block Cipher on Cortex-M3 and RISC-V Microcontrollers," Mathematics, MDPI, vol. 10(22), pages 1-12, November.
    • Handle: RePEc:gam:jmathe:v:10:y:2022:i:22:p:4236-:d:971193
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