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An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks

Author

Listed:
  • Maurizio Capra

    (Department of Electrical, Electronics and Telecommunication Engineering, Politecnico di Torino, 10129 Torino, Italy)

  • Beatrice Bussolino

    (Department of Electrical, Electronics and Telecommunication Engineering, Politecnico di Torino, 10129 Torino, Italy)

  • Alberto Marchisio

    (Embedded Computing Systems, Institute of Computer Engineering, Technische Universität Wien (TU Wien), 1040 Vienna, Austria)

  • Muhammad Shafique

    (Embedded Computing Systems, Institute of Computer Engineering, Technische Universität Wien (TU Wien), 1040 Vienna, Austria)

  • Guido Masera

    (Department of Electrical, Electronics and Telecommunication Engineering, Politecnico di Torino, 10129 Torino, Italy)

  • Maurizio Martina

    (Department of Electrical, Electronics and Telecommunication Engineering, Politecnico di Torino, 10129 Torino, Italy)

Abstract

Deep Neural Networks (DNNs) are nowadays a common practice in most of the Artificial Intelligence (AI) applications. Their ability to go beyond human precision has made these networks a milestone in the history of AI. However, while on the one hand they present cutting edge performance, on the other hand they require enormous computing power. For this reason, numerous optimization techniques at the hardware and software level, and specialized architectures, have been developed to process these models with high performance and power/energy efficiency without affecting their accuracy. In the past, multiple surveys have been reported to provide an overview of different architectures and optimization techniques for efficient execution of Deep Learning (DL) algorithms. This work aims at providing an up-to-date survey, especially covering the prominent works from the last 3 years of the hardware architectures research for DNNs. In this paper, the reader will first understand what a hardware accelerator is, and what are its main components, followed by the latest techniques in the field of dataflow, reconfigurability, variable bit-width, and sparsity.

Suggested Citation

  • Maurizio Capra & Beatrice Bussolino & Alberto Marchisio & Muhammad Shafique & Guido Masera & Maurizio Martina, 2020. "An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks," Future Internet, MDPI, vol. 12(7), pages 1-22, July.
    • Handle: RePEc:gam:jftint:v:12:y:2020:i:7:p:113-:d:381228
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    References listed on IDEAS

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    1. Maurizio Capra & Riccardo Peloso & Guido Masera & Massimo Ruo Roch & Maurizio Martina, 2019. "Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World," Future Internet, MDPI, vol. 11(4), pages 1-25, April.
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    Cited by:

    1. Scott Robbins & Aimee van Wynsberghe, 2022. "Our New Artificial Intelligence Infrastructure: Becoming Locked into an Unsustainable Future," Sustainability, MDPI, vol. 14(8), pages 1-11, April.

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