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Test Methodology for Short-Circuit Assessment and Safe Operation Identification for Power SiC MOSFETs

Author

Listed:
  • Joao Oliveira

    (IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France)

  • Jean-Michel Reynes

    (IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France)

  • Hervé Morel

    (CNRS, INSA Lyon, Université Claude Bernard Lyon 1, Ecole Centrale de Lyon, Ampère, UMR5005, 69621 Villeurbanne, France)

  • Pascal Frey

    (IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France)

  • Olivier Perrotin

    (IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France
    Alter Technology France, 2 Rue des Satellites, 31520 Ramonville-Saint-Agne, France)

  • Laurence Allirand

    (IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France
    Vitesco Technologies, 40 Av. du Général de Croutte, 31100 Toulouse, France)

  • Stéphane Azzopardi

    (IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France
    Safran Tech, Rue des Jeunes Bois, 78117 Chateaufort, France)

  • Michel Piton

    (IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France
    Alstom, 50 Rue du Dr Guinier, 65600 Séméac, France)

  • Fabio Coccetti

    (IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France)

Abstract

The short-circuit (SC) immunity of power silicon carbide (SiC) MOSFETs is critical for high-reliability applications, where robust monitoring and protection strategies are essential to ensure system safety. Despite their superior voltage blocking capabilities and high energy efficiency, SiC MOSFETs exhibit greater sensitivity to SC-induced degradation compared to their silicon counterparts. This increased vulnerability necessitates the precise assessment of the key SC performance metrics, such as short-circuit withstand time ( T S C W T ), as well as a deeper understanding of the failure mechanisms. In this study, a comprehensive experimental methodology for evaluating the SC behavior of SiC MOSFETs is presented and validated using industrial references. The investigation further explores the concept of a Safe Operating Area (SOA) under SC conditions, highlighting the significant impact of quasi-simultaneous SC events on device lifetime. Additionally, an application case study demonstrates how these events can drastically reduce the device’s lifespan.

Suggested Citation

  • Joao Oliveira & Jean-Michel Reynes & Hervé Morel & Pascal Frey & Olivier Perrotin & Laurence Allirand & Stéphane Azzopardi & Michel Piton & Fabio Coccetti, 2024. "Test Methodology for Short-Circuit Assessment and Safe Operation Identification for Power SiC MOSFETs," Energies, MDPI, vol. 17(21), pages 1-20, November.
  • Handle: RePEc:gam:jeners:v:17:y:2024:i:21:p:5476-:d:1512169
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