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Optimized Modulation Method for Common-Mode Voltage Reduction in H7 Inverter

Author

Listed:
  • Belete Belayneh Negesse

    (Department of Electrical and Computer Engineering, Pusan National University, 2 Busandaehak-ro 63beon-gil, Geumjeong-gu, Busan 46241, Korea)

  • Chang-Hwan Park

    (Department of Electrical and Computer Engineering, Pusan National University, 2 Busandaehak-ro 63beon-gil, Geumjeong-gu, Busan 46241, Korea)

  • Seung-Hwan Lee

    (Living Appliance Control Research Division of LG Electronics, 84 Wanam-ro, Seongsan-gu, Changwon 51554, Korea)

  • Seon-Woong Hwang

    (Department of Electrical and Computer Engineering, Pusan National University, 2 Busandaehak-ro 63beon-gil, Geumjeong-gu, Busan 46241, Korea)

  • Jang-Mok Kim

    (Department of Electrical and Computer Engineering, Pusan National University, 2 Busandaehak-ro 63beon-gil, Geumjeong-gu, Busan 46241, Korea)

Abstract

The three-phase H7 inverter topology installs an additional power semiconductor switch to the positive or negative node of the DC-link for reducing the common-mode voltage (CMV) by disconnecting the inverter from the DC source during the zero-voltage vectors. The conventional CMV reduction method for the three-phase H7 inverter uses modified discontinuous pulse width modulation (MDPWM) and generates a switching signal for the additional switch using logical operations. However, the conventional method is unable to eliminate the CMV for the entire dwell time of the zero-voltage vectors. It only has the effect of reducing the CMV in a limited area of the space vector where the V 7 zero voltage vector is applied. Therefore, this paper proposes an optimized modulation method that can reduce the CMV during the entire dwell time of zero-voltage vectors. The proposed method moves the switching patterns by adding an offset voltage to guarantee that only one kind of zero-voltage vector, V 7 , is applied in the system. It then turns off the seventh switch only during the zero-voltage vector to disconnect the inverter from the DC source. As a result, the CMV and the leakage current are attenuated for the entire dwell time of the zero-voltage vector. Simulation and experimental results confirm the validity of the proposed method.

Suggested Citation

  • Belete Belayneh Negesse & Chang-Hwan Park & Seung-Hwan Lee & Seon-Woong Hwang & Jang-Mok Kim, 2021. "Optimized Modulation Method for Common-Mode Voltage Reduction in H7 Inverter," Energies, MDPI, vol. 14(19), pages 1-17, October.
    • Handle: RePEc:gam:jeners:v:14:y:2021:i:19:p:6409-:d:651239
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    Cited by:

    1. Truong-Duy Duong & Minh-Khai Nguyen & Tan-Tai Tran & Dai-Van Vo & Young-Cheol Lim & Joon-Ho Choi, 2022. "Topology Review of Three-Phase Two-Level Transformerless Photovoltaic Inverters for Common-Mode Voltage Reduction," Energies, MDPI, vol. 15(9), pages 1-18, April.

    More about this item

    Keywords

    common-mode voltage; zero-voltage vector; H7 inverter; PMSM;
    All these keywords.

    JEL classification:

    • H7 - Public Economics - - State and Local Government; Intergovernmental Relations

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