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Application of High-Frequency Leakage Current Model for Characterizing Failure Modes in Digital Logic Gates

Author

Listed:
  • Zahra Abedi

    (Department of Electrical & Computer Engineering, University of New Mexico, Albuquerque, NM 87131, USA)

  • Sameer Hemmady

    (Department of Electrical & Computer Engineering, University of New Mexico, Albuquerque, NM 87131, USA)

  • Thomas Antonsen

    (Departments of Electrical and Computer Engineering, Physics, University of Maryland, College Park, MD 20742, USA)

  • Edl Schamiloglu

    (Department of Electrical & Computer Engineering, University of New Mexico, Albuquerque, NM 87131, USA)

  • Payman Zarkesh-Ha

    (Department of Electrical & Computer Engineering, University of New Mexico, Albuquerque, NM 87131, USA)

Abstract

In this paper, a predictive model is developed to characterize the impact of high-frequency electromagnetic interference (EMI) on the leakage current of CMOS integrated circuits. It is shown that the frequency dependence can be easily described by a transfer function that depends only on a few dominant parasitic elements. The developed analytical model is successfully compared against measurement data from devices fabricated using 180 nm, 130 nm, and 65 nm standard CMOS processes through TSMC. Based on the predictive model, the impact of EMI on leakage current in a CMOS inverter is reduced by increasing the frequency from 10 MHz to 4 GHz.

Suggested Citation

  • Zahra Abedi & Sameer Hemmady & Thomas Antonsen & Edl Schamiloglu & Payman Zarkesh-Ha, 2021. "Application of High-Frequency Leakage Current Model for Characterizing Failure Modes in Digital Logic Gates," Energies, MDPI, vol. 14(10), pages 1-11, May.
    • Handle: RePEc:gam:jeners:v:14:y:2021:i:10:p:2906-:d:556654
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