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A New Configuration of Three-Level ZSI Using Transistor Clamped Topology

Author

Listed:
  • Santosh Sonar

    (Electrical and Instrumentation Engineering Department, Thapar Institute of Engineering and Technology, Patiala 147004, India)

Abstract

In this paper, a three-level ZSI (impedance source inverter) based on transistor clamped theory is proposed. It uses the least number of switch counts and associated gate circuitry among all existing topologies of three-level ZSI without any performance degradation. The existing three-level ZSI topologies require three power switches to be turned ON for upper-lower shoot-through (ULST), and four power switches to be turned ON for full dc-link shoot-through (FST). However, with the proposed configuration, upper–lower shoot-through (ULST) and full dc-link shoot-through (FST) is inserted by turning ON only two power semiconductors. A comparison between diode clamped, transistor clamped, and t-type is presented. The proposed topology can realize any of the existing sine-triangle- or space vector-based PWM (pulse width modulation) schemes, and all existing configurations of three-level ZSI can merge into the proposed inverter configuration.

Suggested Citation

  • Santosh Sonar, 2020. "A New Configuration of Three-Level ZSI Using Transistor Clamped Topology," Energies, MDPI, vol. 13(6), pages 1-16, March.
    • Handle: RePEc:gam:jeners:v:13:y:2020:i:6:p:1469-:d:334927
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