Characterization of SiO 2 /4H-SiC Interfaces in 4H-SiC MOSFETs: A Review

This paper gives an overview on some state-of-the-art characterization methods of SiO 2 /4H-SiC interfaces in metal oxide semiconductor field effect transistors (MOSFETs). In particular, the work compares the benefits and drawbacks of different techniques to assess the physical parameters describing the electronic properties and the current transport at the SiO 2 /SiC interfaces (interface states, channel mobility, trapping phenomena, etc.). First, the most common electrical characterization techniques of SiO 2 /SiC interfaces are presented (e.g., capacitance- and current-voltage techniques, transient capacitance, and current measurements). Then, examples of electrical characterizations at the nanoscale (by scanning probe microscopy techniques) are given, to get insights on the homogeneity of the SiO 2 /SiC interface and the local interfacial doping effects occurring upon annealing. The trapping effects occurring in SiO 2 /4H-SiC MOS systems are elucidated using advanced capacitance and current measurements as a function of time. In particular, these measurements give information on the density (~10 11 cm −2 ) of near interface oxide traps (NIOTs) present inside the SiO 2 layer and their position with respect to the interface with SiC (at about 1–2 nm). Finally, it will be shown that a comparison of the electrical data with advanced structural and chemical characterization methods makes it possible to ascribe the NIOTs to the presence of a sub-stoichiometric SiO x layer at the interface.