Design error simulation based on error modeling and sampling techniques

Digital system design and verification becomes more critical as systems grow in size and complexity. Also, simulation of digital systems become more costly in time and resources as systems get larger. This paper presents an effective simulation methodology for design error simulation using error modeling and sampling techniques, so that the simulation time can be reduced and efficient error coverage obtained. In this methodology, the first step is the generation of design error models. These are defined as design changes that cause a different output value from the desired value, for some input pattern. The second part of the system utilizes an error simulation methodology for functional level design models. The third part of the system deals with the automatic generation of design error test patterns for errors that are not detected by user supplied or heuristically generated patterns. The fourth phase of the methodology involves statistical sampling techniques which result in the simulation of only a small subset of the total design errors or test patterns and, hence, significantly reduces the cost of design error coverage analysis.