IDEAS home Printed from https://ideas.repec.org/a/bjc/journl/v9y2022i5p77-81.html
   My bibliography  Save this article

Dual Quaternion Hardware Accelerator for RISC-V based System

Author

Listed:
  • Rajeshwari B

    (Department of Electronics and Communication, PES University, India)

  • Rithvik Kumar

    (Department of Electronics and Communication, PES University, India)

  • Shweta P Hegde

    (Department of Electronics and Communication, PES University, India)

  • Manav Eswar Prasad

    (Department of Electronics and Communication, PES University, India)

  • Vandhya D M

    (Department of Electronics and Communication, PES University, India)

  • Bajrangabali B

    (Department of Electronics and Communication, PES University, India)

Abstract

In this work, a hardware accelerator has been developed for a RISC-V processor. The ‘Parashu’ Shakti processor is the SoC of choice for application testing and development. The IP is designed to speed up applications involving dual quaternion operations. Our module primarily aids dual quaternion multiplication which further helps with other complex operations like translation, rotation and transformation. Two solutions have been proposed for the same, i.e. either a quaternion IP if power and resource utilization is a concern, or a dual quaternion IP if performance gain is the primary objective. The latter is however at the expense of relatively more resource utilization. The former IP takes longer execution time to perform the same task but is more versatile since it can be used in applications involving both quaternion and dual quaternion operations.

Suggested Citation

  • Rajeshwari B & Rithvik Kumar & Shweta P Hegde & Manav Eswar Prasad & Vandhya D M & Bajrangabali B, 2022. "Dual Quaternion Hardware Accelerator for RISC-V based System," International Journal of Research and Scientific Innovation, International Journal of Research and Scientific Innovation (IJRSI), vol. 9(5), pages 77-81, May.
    • Handle: RePEc:bjc:journl:v:9:y:2022:i:5:p:77-81
    as

    Download full text from publisher

    File URL: https://www.rsisinternational.org/journals/ijrsi/digital-library/volume-9-issue-5/77-81.pdf
    Download Restriction: no
    File URL: https://www.rsisinternational.org/virtual-library/papers/dual-quaternion-hardware-accelerator-for-risc-v-based-system/
    Download Restriction: no
    ---><---

    More about this item

    Statistics

    Access and download statistics

    Corrections

    All material on this site has been provided by the respective publishers and authors. You can help correct errors and omissions. When requesting a correction, please mention this item's handle: RePEc:bjc:journl:v:9:y:2022:i:5:p:77-81. See general information about how to correct material in RePEc.

    If you have authored this item and are not yet registered with RePEc, we encourage you to do it here. This allows to link your profile to this item. It also allows you to accept potential citations to this item that we are uncertain about.

    We have no bibliographic references for this item. You can help adding them by using this form .

    If you know of missing items citing this one, you can help us creating those links by adding the relevant references in the same way as above, for each refering item. If you are a registered author of this item, you may also want to check the "citations" tab in your RePEc Author Service profile, as there may be some citations waiting for confirmation.

    For technical questions regarding this item, or to correct its authors, title, abstract, bibliographic or download information, contact: Dr. Renu Malsaria (email available below). General contact details of provider: https://rsisinternational.org/journals/ijrsi/ .

    Please note that corrections may take a couple of weeks to filter through the various RePEc services.

    IDEAS is a RePEc service. RePEc uses bibliographic data supplied by the respective publishers.