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Power Optimized Gate Finfet Based SRAM Cell Design to Enhance the Read Access and Improve the Writing Speed

Author

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  • Dr. M. Kamaraju

    (Sesahadri Rao Gudlavalleru Engineering College, Gudlavalleru, Andhra Pradesh, India)

  • M. Prince dany

    (Sesahadri Rao Gudlavalleru Engineering College, Gudlavalleru, Andhra Pradesh, India)

  • M. Gopi Sankar

    (Sesahadri Rao Gudlavalleru Engineering College, Gudlavalleru, Andhra Pradesh, India)

  • K. Gnana Siri

    (Sesahadri Rao Gudlavalleru Engineering College, Gudlavalleru, Andhra Pradesh, India)

  • M. Rupa Sri

    (Sesahadri Rao Gudlavalleru Engineering College, Gudlavalleru, Andhra Pradesh, India)

Abstract

Multi-port SRAM is important for storing, sharing data quickly into the modern processors. This study focuses on 6T SRAM cells designed with 7nm FinFET technology, which is known for its fast operation, low power usage, and high efficiency compared to traditional CMOS designs. The performance of these SRAMs was tested under various conditions, including supply voltages from 0.1V to 1.0V and frequencies ranging from 10 MHz to 2 GHz, using the Microwind 3.8 simulation tool. Key metrics like write time, access time, and power consumption were analyzed, showing that FinFET-based designs perform better overall, making them a great choice for modern electronic systems.

Suggested Citation

  • Dr. M. Kamaraju & M. Prince dany & M. Gopi Sankar & K. Gnana Siri & M. Rupa Sri, 2025. "Power Optimized Gate Finfet Based SRAM Cell Design to Enhance the Read Access and Improve the Writing Speed," International Journal of Research and Scientific Innovation, International Journal of Research and Scientific Innovation (IJRSI), vol. 12(2), pages 643-652, February.
    • Handle: RePEc:bjc:journl:v:12:y:2025:i:2:p:643-652
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