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Inverter Dead-Time Elimination for Reducing Harmonic Distortion and Improving Power Quality

Author

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  • R Narmatha
  • T Govindaraj

Abstract

Numerous studies have been presented to eliminate dead-time effect. This paper will present a dead-time elimination scheme for a sinusoidal pulse width modulation (SPWM) controlled inverter. In comparison to using expensive current sensor, this method precisely determine the load current polarity by detecting the terminal voltage of the antiparallel diode of power devices. The presented scheme includes the freewheeling current polarity detection circuit and the PWM control generator without dead-time. This method significantly reduces the output voltage loss, harmonic distortion and improves quality of power. Simulation results are given to demonstrate the effectiveness of the dead-time elimination scheme.

Suggested Citation

  • R Narmatha & T Govindaraj, 2013. "Inverter Dead-Time Elimination for Reducing Harmonic Distortion and Improving Power Quality," Journal of Asian Scientific Research, Asian Economic and Social Society, vol. 3(3), pages 247-257.
    • Handle: RePEc:asi:joasrj:v:3:y:2013:i:3:p:247-257:id:3472
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