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12-Bit High Speed Direct Digital Frequency Synthesizer Based on Pipelining Phase Accumulator Design

Author

Listed:
  • Salah Hasan Ibrahim
  • Sawal Hamid Md Ali
  • Md. Shabiul Islam

Abstract

This paper presents high speed direct digital frequency synthesizer (DDFS) based on pipelining phase accumulator (PA). The proposed 12-bit PA contains three pipelining stages with 4-bit carry-lookahead adder (CLA) with the carries ripple between these stages. Comparing results between similar phase accumulator designed with ripple carry adder on, Cyclone III FPGA platform reveals that the proposed phase accumulator runs approximately 10.5% and 13% faster than conventional phase accumulator in approximately for 12-bit and 18-bit respectively.

Suggested Citation

  • Salah Hasan Ibrahim & Sawal Hamid Md Ali & Md. Shabiul Islam, 2012. "12-Bit High Speed Direct Digital Frequency Synthesizer Based on Pipelining Phase Accumulator Design," Journal of Asian Scientific Research, Asian Economic and Social Society, vol. 2(11), pages 667-672.
    • Handle: RePEc:asi:joasrj:v:2:y:2012:i:11:p:667-672:id:3411
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